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PTH03050YAZT

更新时间： 2024-01-05 15:39:17
品牌 Logo 应用领域
德州仪器 - TI 双倍数据速率
页数 文件大小 规格书
18页 1023K
描述
6 A 3.3-V Input Bus Termination Power Module for DDR/QDR Memory 6-Surface Mount Module -40 to 85

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PTH03050YAZT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：,
针数：6Reach Compliance Code：compliant
ECCN代码：EAR99风险等级：5.17
其他特性：REMOTE SHUTDOWN模拟集成电路 - 其他类型：DC-DC REGULATED POWER SUPPLY MODULE
认证：UL, CSA效率（主输出）：88%
高度：8500 mm最大输入电压：3.65 V
最小输入电压：2.95 V标称输入电压：3 V
JESD-30 代码：R-XDMA-X6JESD-609代码：e1
长度：22.1 mm湿度敏感等级：3
功能数量：1输出次数：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C最大输出电流：8 A
标称输出电压：1.25 V封装主体材料：UNSPECIFIED
封装形状：RECTANGULAR封装形式：MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）：260认证状态：Not Qualified
纹波电压（主输出）：0.007 Vrms子类别：Power Supply Modules
表面贴装：NO技术：HYBRID
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：UNSPECIFIED
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大总功率输出：10 W微调/可调输出：YES
宽度：12.57 mmBase Number Matches：1

PTH03050YAZT 数据手册

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PTH03050Y  
PTH05050Y  
PTH12050Y  
www.ti.com  
SLTS221A–MARCH 2004–REVISED OCTOBER 2005  
6-A NON-ISOLATED DDR/QDR  
MEMORY BUS TERMINATION MODULES  
FEATURES  
•
•
50 W/in3 Power Density  
Safety Agency Approvals:  
UL/cUL60950, EN60950, VDE  
•
VTT Bus Termination Output  
(Output Tracks the System VREF  
)
•
•
•
•
•
•
•
•
6 A Output Current (8 A Peak)  
3.3-V, 5-V or 12-V Input Voltage  
DDR and QDR Compatible  
On/Off Inhibit (for VTT Standby)  
Undervoltage Lockout  
Operating Temperature: –40°C to 85°C  
Efficiencies up to 88%  
Output Overcurrent Protection (Non-Latching,  
Auto-Reset)  
•
Point-of-Load Alliance (POLA™) Compatible  
NOMINAL SIZE =0.87 in x 0.5 in  
(22,1 mm x 12,57 mm)  
DESCRIPTION  
The PTHxx050Y are a series of ready-to-use switching regulator modules from Texas Instruments designed  
specifically for bus termination in DDR and QDR memory applications. Operating from either a 3.3-V, 5-V or 12-V  
input, the modules generate a VTT output that will source or sink up to 6 A of current (8 A transient) to accurately  
track their VREF input. VTT is the required bus termination supply voltage, and VREF is the reference voltage for  
the memory and chipset bus receiver comparators. VREF is usually set to half the VDDQ power supply voltage.  
Both the PTHxx050Y series employs an actively switched synchronous rectifier output to provide state-of-the-art  
stepdown switching conversion. The products are small in size (0.87 in × 0.5 in), and are an ideal choice where  
space, performance, and high efficiency are desired, along with the convenience of a ready-to-use module.  
Operating features include an on/off inhibit and output over-current protection (source mode only). The on/off  
inhibit feature allows the VTT bus to be turned off to save power in a standby mode of operation.  
Package options include both throughhole and surface mount configurations.  
STANDARD APPLICATION  
V
IN  
VDDQ  
VREF  
VTT  
1 k  
1 %  
1
2
3
4
6
5
PTHxx050Y  
(Top View)  
Co  
n
1 k  
1 %  
hf−Ceramic  
Co  
Co  
2
Low1−ESR  
(Required)  
Ceramic  
C
IN  
SSTL−2  
Bus  
(Required)  
(Optional)  
Q1  
BSS138  
Standby  
GND  
(Optional)  
C
= Required Electrolytic Capacitor; 220µF (3.3 ± 5 V Input), 560 µF (12 V Input).  
IN  
Co = Required Low-ESR Electrolyitic Capacitor; 470 µF (3.3 ± 5 V Input), 940 µF (12 V Input).  
1
Co = Ceramic Capacitance for Response to a 3 A (+ 1.5 A) Load Transient; 200 µF (3.3 ± 5 V Input), 400 µF (12 V Input).  
2
Co = Distributed hf-Ceramic Decoupling Capacitors for V bus; as Recommended for DDR Memory Applications.  
n TT  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
POLA is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...18

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