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PSD813F1A-15J PDF预览

PSD813F1A-15J

更新时间: 2024-10-01 14:36:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围集成电路
页数 文件大小 规格书
111页 1131K
描述
128KX8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52, PLASTIC, LCC-52

PSD813F1A-15J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-52
针数:52Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.68Is Samacsys:N
最长访问时间:1.5e-7 nsJESD-30 代码:S-PQCC-J52
JESD-609代码:e0长度:19.1 mm
I/O 线路数量:27端口数量:4
端子数量:52最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 V认证状态:Not Qualified
ROM大小(位):1310720 Bits座面最大高度:4.57 mm
最大待机电流:0.0002 A子类别:Other Microprocessor ICs
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
紫外线可擦:N宽度:19.1 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PSD813F1A-15J 数据手册

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PSD813F1A  
Flash in-system programmable (ISP) peripherals  
for 8-bit MCUs, 5 V  
NOT FOR NEW DESIGN  
FEATURES SUMMARY  
DUAL BANK FLASH MEMORIES  
Figure 1. Packages  
1 Mbit of Primary Flash Memory (8  
Uniform Sectors)  
256 Kbit Secondary EEPROM (4 Uniform  
Sectors)  
Concurrent operation: read from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
16 Kbit SRAM  
PLD WITH MACROCELLS  
Over 3,000 Gates Of PLD: DPLD and  
CPLD  
DPLD - User-defined Internal chip-select  
decoding  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
PLCC52 (J)  
TQFQ64 (U)  
27 RECONFIGURABLE I/Os  
27 individually configurable I/O port pins  
that can be used for the following  
functions (16 I/O ports configurable as  
open-drain outputs):  
MCU I/Os  
PLD I/Os  
Latched MCU address output; and  
Special function I/Os  
ENHANCED JTAG SERIPORT  
HIGH ENDURANCE:  
100,000 Erase/WRITE Cycles of Flash  
Memory  
Built-in JTAGcompliant serial port allows  
full-chip In-System Programmability (ISP)  
Efficient manufacturing allows for easy  
product testing and programming  
10,000 Erase/WRITE Cycles of EEPROM  
1,000 Erase/WRITE Cycles of PLD  
Data Retention: 15-year minimum at 90°C  
(for Main Flash, Boot, PLD and  
Configuration bits).  
PAGE REGISTER  
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256.  
SINGLE SUPPLY VOLTAGE:  
5V 10% for 5V  
PROGRAMMABLE POWER MANAGEMENT  
STANDBY CURRENT AS LOW AS 50µA  
Packages are ECOPACK  
®
October 2008  
Rev 5  
1/111  
This is information on a product still in production but not recommended for new designs.  

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