Datasheet > PPXD3020VMS2R

PPXD3020VMS2R

更新时间： 2022-03-22 02:07:23

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
139页	792K
描述
PXS30 Microcontroller

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数据手册

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PPXD3020VMS2R 数据手册

Introduction

1.4

Feature list

•

High-performance e200z7d dual core

— 32-bit Power Architecture technology CPU

— Up to 180 MHz core frequency

— Dual-issue core

— Variable length encoding (VLE)

— Memory management unit (MMU) with 64 entries

— 16 KB instruction cache and 16 KB data cache

Memory available

•

— Up to 2 MB Code flash memory with ECC

— 64 KB Data flash memory with ECC

— Up to 512 KB on-chip SRAM with ECC

SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection

— Sphere of replication (SoR) for key components

— Redundancy checking units on outputs of the SoR connected to FCCU

— Fault collection and control unit (FCCU)

— Boot-time built-in self-test for memory (MBIST) and logic (LBIST) triggered by hardware

— Boot-time built-in self-test for ADC and flash memory

— Replicated safety-enhanced watchdog timer

— Junction temperature sensor

— Non-maskable interrupt (NMI)

— 16-region memory protection unit (MPU)

— Clock monitoring units (CMU)

— Power management unit (PMU)

— Cyclic redundancy check (CRC) units

Decoupled Parallel mode for high-performance use of replicated cores

Nexus Class 3+ interface

•

Interrupts

— Replicated 16-priority interrupt controller

— Replicated 32-channel eDMA controller

GPIOs individually programmable as input, output, or special function

3 general-purpose eTimer units (6 channels each)

3 FlexPWM units with four 16-bit channels per module

Communications interfaces

•

— 4 LINFlex modules

— 3 DSPI modules with automatic chip select generation

— 4 FlexCAN interfaces (2.0B Active) with 32 message objects

PXS30 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1...3 4 567 8 9...139

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