Datasheet > PPXD2010VMM120R

PPXD2010VMM120R

更新时间： 2022-02-26 10:40:13

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
119页	667K
描述
PXS20 Microcontroller

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PPXD2010VMM120R 数据手册

Introduction

1.5.4

Enhanced Direct Memory Access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation

is used to minimize the overall block size.

The eDMA module provides the following features:

•

16 channels supporting 8-, 16-, and 32-bit value single or block transfers

Support variable sized queues and circular buffered queue

Source and destination address registers independently configured to post-increment or stay constant

Support major and minor loop offset

Support minor and major loop done signals

DMA task initiated either by hardware requestor or by software

Each DMA task can optionally generate an interrupt at completion and retirement of the task

Signal to indicate closure of last minor loop

Transfer control descriptors mapped inside the SRAM

The eDMA controller is replicated for each processor.

1.5.5

On-Chip Flash Memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction

storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory

array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.

The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait

state response at 120 MHz.

The flash memory module provides the following features

•

1 MB of flash memory in unique multi-partitioned hard macro

Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB

EEPROM emulation (in software) within same module but on different partition

16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits

Wait states:

— 3 wait states at 120 MHz

— 2 wait states at 80 MHz

— 1 wait state at 60 MHz

•

Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)

Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations

1-bit error correction, 2-bit error detection

1.5.6

On-Chip SRAM with ECC

The PXS20 SRAM provides a general-purpose single port memory.

ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic

coverage including the array internal address decoder.

The SRAM module provides the following features:

•

System SRAM: 128 KB

PXS20 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

1...6 7 8910 11 12...119

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与PPXD2010VMM120R相关器件

型号	品牌	获取价格	描述	数据表
PPXD2010VMM80R	FREESCALE	获取价格	32-bit Power ArchitectureÂ® Microcontrollers
PPXD2010VVU120R	FREESCALE	获取价格	PXD20 Microcontroller
PPXD2010VVU80R	FREESCALE	获取价格	PXD20 Microcontroller
PPXD2020VMG116R	FREESCALE	获取价格	32-bit Power ArchitectureÂ® Dual Core Microco
PPXD3010VMM1R	FREESCALE	获取价格	PXS30 Microcontroller
PPXD3010VMM2R	FREESCALE	获取价格	PXS30 Microcontroller
PPXD3010VMS1R	FREESCALE	获取价格	PXS30 Microcontroller
PPXD3010VMS2R	FREESCALE	获取价格	PXS30 Microcontroller
PPXD3015VMM1R	FREESCALE	获取价格	PXS30 Microcontroller
PPXD3015VMM2R	FREESCALE	获取价格	PXS30 Microcontroller

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