PMC232/PMS232 Series
12-bit ADC Enhanced FPPATM
8-bit OTP Controller
5-5. Data Memory -- SRAM.........................................................................................................35
5-6. Arithmetic and Logic Unit.....................................................................................................35
5-7. Oscillator and clock..............................................................................................................36
5-7-1. Internal High RC oscillator and Internal Low RC oscillator .........................................36
5-7-2. Chip calibration..........................................................................................................36
5-7-3. IHRC Frequency Calibration and System Clock.........................................................36
5-7-4. External Crystal Oscillator..........................................................................................38
5-7-5. System Clock and LVR level......................................................................................39
5-7-6. System Clock Switching.............................................................................................40
5-8. 16-bit Timer (Timer16) .........................................................................................................41
5-9. 8-bit Timer (Timer2) with PWM generation...........................................................................43
5-9-1. Using the Timer2 to generate periodical waveform ....................................................44
5-9-2. Using the Timer2 to generate 8-bit PWM waveform...................................................46
5-9-3. Using the Timer2 to generate 6-bit PWM waveform...................................................47
5-10. WatchDog Timer................................................................................................................48
5-11. Interrupt .............................................................................................................................49
5-12. Power-Save and Power-Down ...........................................................................................51
5-12-1. Power-Save mode (“stopexe”) .................................................................................51
5-12-2. Power-Down mode (“stopsys”).................................................................................52
5-12-3. Wake-up..................................................................................................................53
5-13. IO Pins...............................................................................................................................54
5-14. Reset and LVR ..................................................................................................................55
5.14.1. Reset .......................................................................................................................55
5.14.2. LVR reset.................................................................................................................55
5-15. VDD/2 bias Voltage Generator...........................................................................................55
5-16. Analog-to-Digital Conversion (ADC) module......................................................................56
5-16-1. The input requirement for AD conversion.................................................................57
5-16-2. Select the ADC bit resolution ...................................................................................58
5-16-3. ADC clock selection.................................................................................................58
5-16-4. AD conversion .........................................................................................................58
5-16-5. Configure the analog pins........................................................................................58
5-16-6. Using the ADC.........................................................................................................59
6. IO Registers ....................................................................................................................60
6-1. ACC Status Flag Register (flag), IO address = 0x00............................................................60
6-2. FPP unit Enable Register (fppen), IO address = 0x01..........................................................60
6-3. Stack Pointer Register (sp), IO address = 0x02 ...................................................................60
6-4. Clock Mode Register (clkmd), IO address = 0x03 ................................................................60
6-5. Interrupt Enable Register (inten), IO address = 0x04 ...........................................................61
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMx232_V104– Dec. 18, 2018
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