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PM8355? PDF预览

PM8355?

更新时间: 2024-01-10 22:20:55
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其他 - ETC /
页数 文件大小 规格书
2页 70K
描述
Short Form PMC-2000791 PM8355 QuadPHY-II 4-Channel 2.125| 2.5 to 3.125 Gbit/s Transceiver with Half-rate Support Short Form Data Sheet [92 kB]

PM8355? 技术参数

是否Rohs认证: 不符合生命周期:Transferred
Reach Compliance Code:compliant风险等级:5.88
数据速率:3125000 MbpsJESD-30 代码:S-PBGA-B289
JESD-609代码:e0湿度敏感等级:3
端子数量:289收发器数量:4
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA289,17X17,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:1.8,1.8/2.5 V认证状态:Not Qualified
子类别:Network Interfaces表面贴装:YES
技术:CMOS电信集成电路类型:ETHERNET TRANSCEIVER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM

PM8355? 数据手册

 浏览型号PM8355?的Datasheet PDF文件第2页 
PM8355  
QuadPHY-II™  
4-Channel 2.125, 2.5, and 3.125 Gbit/s Transceiver with Half-rate Support  
SERIAL I/O  
• Trunking feature de-skews and aligns  
all four channels to form a single  
10 Gbit/s logical link.  
GENERAL DESCRIPTION  
• Redundant high-speed serial I/O  
channels for convenient switching to  
redundant fabric.  
The QuadPHY-II™ is a physical layer  
transceiver ideal for systems requiring  
high-speed point-to-point communi-  
cation links. It is applicable for PMA-  
PMD connections in 10 GE, Infiniband 1  
or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s  
Fibre Channel, as well as high speed  
serial backplanes for high capacity  
systems.  
TEST FEATURES  
• High-speed outputs with optional pre-  
emphasis to drive longer backplanes.  
• High-speed I/O with on-chip  
termination resistors to directly drive  
dual-terminated 50 Ohm lines.  
• High-speed inputs have programmable  
receive equalization to eliminate the  
effects of Inter Symbol Interference  
(ISI).  
• Extensive control of loopback, BIST,  
and operating modes via 802.3  
compliant MDC/MDIO serial interface.  
• On-chip packet generator/checker-  
provides at-speed diagnostics.  
• Built-in error counters per channel.  
• Support for IEEE 1149.1 JTAG testing  
on all pins.  
FEATURES  
GENERAL  
PHYSICAL  
• 10Gbit/s, bi-directional, XAUI to XGMII  
link compatible with IEEE 802.3ae.  
• Four independent 2.125, 2.5 and  
3.125 Gbit/s SERDES for Fibre  
Channel, Infiniband, 10 GE line cards  
and high-speed backplane  
applications.  
• Half/Full rate mode selectable per  
channel.  
• Integrated serializer/ deserializer, clock  
synthesis, clock recovery and 8B/10B  
encode/decode logic.  
• Low-power operation 1.5 W typical  
@ 3.125Gbit/s.  
PARALLEL I/O  
• 10-bit Dual Data Rate (DDR) parallel  
interface.  
• Selectable source simultaneous or  
source synchronous transmit and  
receive parallel interfaces.  
• Convenient output clock for user  
friendly ASIC timing.  
• 1.8V, 0.18 µ standard CMOS  
technology with 2.5 V tolerant I/O.  
• 289-ball CABGA (19 mm x 19 mm  
package).  
APPLICATIONS  
• High speed serial backplanes  
• 10 GE links  
• Fibre Channel transceivers  
• Infiniband transceivers  
• XAUI retimers  
• Interoperates with SSTL2 and 1.8 V  
LVCMOS standard.  
TRUNKING &TIMING  
• Integrated Receive FIFO synchronizes  
incoming data to local clock domain.  
• Intra-system interconnect  
BLOCK DIAGRAM  
PM8355 - QuadPHY-II  
TDOXPA/  
TDOXNA  
Primary Channel  
TXDA [9:0]  
FIFO  
&
/A/ Insert  
Adaptive  
Sampler  
9 or 10  
2
2
8B/10B  
Encoder  
XAUI Transmit  
Serializer  
XGMII Parallel Input  
TXCLK  
TDOYPA/  
TDOYNA  
Secondary Channel  
Serial  
Loopback  
Parallel  
Loopback  
RDIXPA/  
RDIXNA  
RXDA [9:0]  
Primary Channel  
De-  
Serializer  
& Byte  
Align  
FIFO &  
Trunking  
Logic  
9 or 10  
2
10B/8B  
Decoder  
Clock  
Recovery  
XAUI Receive  
XGMII Parallel Output  
RXCLKA  
RDIYPA/  
RDIYNA  
2
Secondary Channel  
Channel A  
Channel B  
Channel C  
Channel D  
Common Control  
Logic  
Clock  
Synthesis  
RESET, MDIO/MDC  
Mode Strapping Pins  
JTAG Interface, BIST  
pins  
PMC-2000791 (P6)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2002  

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