Datasheet > PM8357-NI-P

PM8357-NI-P

更新时间： 2024-02-10 19:58:06

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	54K
描述
Telecom IC,

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PM8357-NI-P 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	compliant	风险等级：	5.76
湿度敏感等级：	3	Base Number Matches：	1

PM8357-NI-P 数据手册

PM8357

QuadPHY XR

Preliminary

Low Power 4 Channel Bi-directional 1.2 - 3.2 Gbit/s Retimer

• On-chip packet generator/checker

provides at-speed diagnostics.

• Pin-configurable for standalone

operation.

FEATURES

GENERAL

• Built-in error counters per channel.

• Support for IEEE 1149.1 JTAG testing on

all pins.

• Comprehensive evaluation platform for

easy customer qualification

• Integrated serializer/deserializer, clock

synthesis, clock recovery and 8B/10B

encode/decode logic.

• Supports differential AC-coupled PECL-

level REFCLK.

• Low power, 4 channel, bi-directional,

full duplex, 1.2 - 3.2 Gbit/s retimer

compliant with the 10 Gigabit Ethernet

(10GE) and proposed 10 Gigabit Fibre

Channel (10GFC) standards.

• Ideal for 10GBase-CX4 (IEEE 802.3ak)

uplinks and stacking interfaces in

ethernet switches.

• Ideal for 10GE, 10GFC, and InfiniBand

applications for extending the reach of

high-speed serial links across a

backplane.

• Four channels can be trunked to form

one logical link for XAUI retimer

applications.

• 8B/10B encoders/decoders can be

bypassed for retiming of scrambled

NRZ data streams.

HIGH-SPEED SERIAL INTERFACE

PHYSICAL CHARACTERISTICS

• 1.2 V/2.5 V, 0.13 µm CMOS technology.

• 196-pin CABGA (15 mm x 15 mm).

• 1.5 W typical power at 3.2 Gbit/s.

• Programmable receiver equalization to

minimize the effects of Inter Symbol

Interference (ISI)

• Programmable transmit pre-emphasis

to counteract dielectric losses and allow

maximum reach on printed circuit

boards.

• Integrated termination resistors to

directly drive 100 ohm differential

traces.

APPLICATIONS

• High-speed Backplane Retimer.

• Board-to-board Interconnect.

• XAUI Link Extender.

• 10GBase-CX4/LX4 Modules

• HD-SDI (HDTV) Video Switch/Routers

TEST FEATURES

• Extensive control of loopback, BIST

and operating modes via 802.3ae-

compliant MDC/MDIO serial interface

(1.2 V compliant).

• Supports non-blocking cross-connect to

enable flexible configuration as a re-

timer or cross-connect.

BLOCK DIAGRAM

QuadPHY XR

RX XAUI Port A

DL0A_P/N

TX XAUI Port B

REFX A

TEFX B

Clock

Byte

SL0B_P/N

SL1B_P/N

SL2B_P/N

SL3B_P/N

DL1A_P/N

DL2A_P/N

DL3A_P/N

Recov &

Deserialise

RASIO-3G

Align and

10B/8B

Decoder

FIFO &

Trunking

Serializer

RASIO-3G

8B/10B

Encoder

FIFO

XC16

Cross

bar

RX XAUI Port B

TX XAUI Port A

TEFX A

REFX B

SL0A_P/N

SL1A_P/N

SL2A_P/N

SL3A_P/N

Byte

Align and

10B/8B

Clock

Recov &

Deserialise

RASIO-3G

DL0B_P/N

DL1B_P/N

DL2B_P/N

DL3B_P/N

FIFO &

Trunking

Serializer

RASIO-3G

8B/10B

Encoder

FIFO

Decoder

RX_FAULT_A

RX_FAULT_B

TX_FAULT_A

RX_FAULT_B

SD_A

SD_B

Management

Interface

Clock

Synthesizer

JTAG

Test Access Port

EN_SLPBK_A

EN_SLPBK_B

Common Control Logic

PMC-2012585

Issue 4

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,

AND FOR ITS CUSTOMERS’ INTERNAL USE

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