PI90SD1636A

更新时间： 2024-02-01 16:43:48

品牌	Logo	应用领域
百利通 - PERICOM		以太网
页数	文件大小	规格书
15页	526K
描述
SERDES Gigabit Ethernet Transceiver

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技术参数
数据手册

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PI90SD1636A 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP, QFP64,.6SQ,32	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.77
Is Samacsys：	N	数据速率：	1250000 Mbps
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	64
收发器数量：	1	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP64,.6SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Network Interfaces	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

PI90SD1636A 数据手册

PI90SD1636A

SERDES Gigabit Ethernet Transceiver

Functional Block Description

Input Data Latch

The input data latch block latches the 10-bit TTL input parallel byte, TX<9:0>, on the rising edge of the 125 MHz user-provided

TX_CLK into the holding registers.

Parallel-to-Serial Converter

The received 10-bit TTL parallel input byte is converted to serial PECL level data stream by the parallel-to-serial block, and is trans-

mitted differentially to the line driver block at 1.25 Gbps. The 8b/10b encoded data is transmitted sequentially with bit 0 being sent

ﬁrst.

Clock Generator

The 125 MHz signal used for clocking the serial outputs is generated by the TX PLL block based on the user-provided TX_CLK.

This clock should have a ±100 ppm tolerance.

Internal Loopback

When EWRAP is set to a logic HIGH, the serial data stream generated by the transmitter is looped back to the receiver path, instead

of going out to the DOUT± pins. When in loopback mode, a static logic 1 is transmitted at the line driver (DOUT+ is HIGH and

DOUT- is LOW).

Signal Detect

Signal detect block is used to sense the serial input data stream at pins DIN±. If the serial input is lower than 50mV differentially, this

block deasserts SIG_DET and sets the output, RX<9:0>, to all logic ones. When the serial input at pins DIN± is greater than 50mV,

the signal is directed to the receive path.

Equalizer and Slicer

The signal received from the line (DIN± pins) is distorted by the cable bandwidth. In order to maintain a low bit-error rate, an equalizer

is used to compensate for the signal loss. The slicer recovers the differential low-level signal to a CMOS-level single-ended signal,

for clock recovery and data re-timing.

Clock Recovery

The serial input data stream contains both data and clock. The clock recovery block is used to extract both data and clocks from this

input. In addition to data, two clocks of 62.5 MHz are recovered.

PS8641

10/14/04

1...3 4 567 8 9...15

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与PI90SD1636A相关器件

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PI90SD1636AFC	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格
PI90SD1636AFCE	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格
PI90SD1636AFD	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格
PI90SD1636AFDE	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格
PI90SD1636C	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格
PI90SD1636CFC	PERICOM	SERDES Gigabit Ethernet Transceiver	获取价格

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