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PI90LV03TEX

更新时间： 2024-02-05 01:41:28
品牌 Logo 应用领域
百利通 - PERICOM 中继器
页数 文件大小 规格书
7页 319K
描述
SOTiny LVDS Repeater

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中文翻译

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PI90LV03TEX 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT-23
包装说明：LSSOP, TSOP6,.11,37针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.71
差分输出：YES驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：R-PDSO-G6
JESD-609代码：e3长度：2.9 mm
湿度敏感等级：1功能数量：1
端子数量：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：TSOP6,.11,37
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：1座面最大高度：1.45 mm
子类别：Line Driver or Receivers最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN (787)端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40最大传输延迟：6 ns
宽度：1.625 mmBase Number Matches：1

PI90LV03TEX 数据手册

 浏览型号PI90LV03TEX的Datasheet PDF文件第2页浏览型号PI90LV03TEX的Datasheet PDF文件第3页浏览型号PI90LV03TEX的Datasheet PDF文件第4页浏览型号PI90LV03TEX的Datasheet PDF文件第5页浏览型号PI90LV03TEX的Datasheet PDF文件第6页浏览型号PI90LV03TEX的Datasheet PDF文件第7页 
PI90LV03/PI90LVB03  
SOTiny™ LVDS Repeater  
Features  
Description  
•
•
•
•
•
•
•
•
Complies with ANSI/TIA/EIA-644-A LVDS standard  
PI90LV03 and PI90LVB03 are single LVDS Repeaters that use  
low-voltage differential signaling (LVDS) to support data rates up  
to 660 Mbps. The PI90LVB03 features high-drive output. Both  
products are designed for applications requiring high-speed, low-  
power consumption, low-noise generation, and a small package.  
LVDS receiver inputs accept LVPECL signals  
Low jitter 660 Mbps fully differential data path  
Bus-Terminal ESD exceeds 2kV  
Single +3.3V supply voltage operation  
Receiver Differential Input Voltage Threshold < ±100mV  
Receiver open-circuit failsafe  
Low-Voltage Differential Signaling with typical Output Volt-  
ages of 350mV into:  
– 100Ω Load (PI90LV03)  
The LVDS Repeaters take an LVDS input signal and provide an  
LVDS output to address various interface logic requirements such  
as signal isolation, repeater, stub length, and Optical Transceiver  
Modules. In many large systems, signals are distributed across  
backplanes, and the distance between the transmission line and the  
unterminated receivers are one of the limiting factors for system  
speed. The buffers can be used to reduce the ‘stub length’ by stra-  
tegic device placement along the trace length. They can improve  
system performance by allowing the receiver to be placed very  
close to the main transmission line or very close to the connector  
on the card. Longer traces to the LVDS receiver can then be placed  
after the buffer.  
– 50Ω Load (PI90LVB03)  
Typical Propagation Delay Times of 1.5ns  
Typical Power Dissipation of 20mW @ 200 MHz  
•
•
•
•
•
Outputs are High Impedance with V < 1.5V  
CC  
Industrial Temperature Range: –40°C to 85°C  
Packaging:  
- 6-pin space-saving SOT-23 (T)  
The buffer’s wide input dynamic range enables them to receive dif-  
ferentialsignalsfromLVPECLandLVDSsources.Thedevicescan  
be used as compact high-speed serial translators between LVPECL  
and LVDS data lines. The differential translation provides a simple  
waytomixandmatchOpticalTransceiverICsfromvariousvendors  
without redesigning the interfaces.  
Function Table  
Inputs  
Outputs  
V
= V - V  
V - V  
Y Z  
ID  
A
B
V
> 50mV  
H
X
L
ID  
50mV < V < 50mV  
ID  
V
≤ -50mV  
Open  
ID  
Applications  
H
The PI90LV03 and PI90LVB03 provide differential translation  
between LVDS and PECL devices for high-speed, point-to-point  
interface and telecom applications:  
Notes:  
1. H = high level; L = low level; X = indeterminate  
Block Diagram  
– ATM  
– SONET/SDH  
– Switches  
– Routers  
5
4
1
2
A
B
Y
– Add-Drop Multiplexers  
Z
High-Speed Differential Cable Repeater Application  
Pin Configuration  
Any LVDS R  
R = Z  
O
T
LVDS Repeater  
X
R
= Z  
O
T
VDD  
A
B
6
5
4
1
2
3
Z
Z
O
T
O
X
Y
Z
GND  
PS8660A  
07/07/04  
1
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中文翻译

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