PI90LV03/PI90LVB03
SOTiny™ LVDS Repeater
Features
Description
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Complies with ANSI/TIA/EIA-644-A LVDS standard
PI90LV03 and PI90LVB03 are single LVDS Repeaters that use
low-voltage differential signaling (LVDS) to support data rates up
to 660 Mbps. The PI90LVB03 features high-drive output. Both
products are designed for applications requiring high-speed, low-
power consumption, low-noise generation, and a small package.
LVDS receiver inputs accept LVPECL signals
Low jitter 660 Mbps fully differential data path
Bus-Terminal ESD exceeds 2kV
Single +3.3V supply voltage operation
Receiver Differential Input Voltage Threshold < ±100mV
Receiver open-circuit failsafe
Low-Voltage Differential Signaling with typical Output Volt-
ages of 350mV into:
– 100Ω Load (PI90LV03)
The LVDS Repeaters take an LVDS input signal and provide an
LVDS output to address various interface logic requirements such
as signal isolation, repeater, stub length, and Optical Transceiver
Modules. In many large systems, signals are distributed across
backplanes, and the distance between the transmission line and the
unterminated receivers are one of the limiting factors for system
speed. The buffers can be used to reduce the ‘stub length’ by stra-
tegic device placement along the trace length. They can improve
system performance by allowing the receiver to be placed very
close to the main transmission line or very close to the connector
on the card. Longer traces to the LVDS receiver can then be placed
after the buffer.
– 50Ω Load (PI90LVB03)
Typical Propagation Delay Times of 1.5ns
Typical Power Dissipation of 20mW @ 200 MHz
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Outputs are High Impedance with V < 1.5V
CC
Industrial Temperature Range: –40°C to 85°C
Packaging:
- 6-pin space-saving SOT-23 (T)
The buffer’s wide input dynamic range enables them to receive dif-
ferentialsignalsfromLVPECLandLVDSsources.Thedevicescan
be used as compact high-speed serial translators between LVPECL
and LVDS data lines. The differential translation provides a simple
waytomixandmatchOpticalTransceiverICsfromvariousvendors
without redesigning the interfaces.
Function Table
Inputs
Outputs
V
= V - V
V - V
Y Z
ID
A
B
V
> 50mV
H
X
L
ID
50mV < V < 50mV
ID
V
≤ -50mV
Open
ID
Applications
H
The PI90LV03 and PI90LVB03 provide differential translation
between LVDS and PECL devices for high-speed, point-to-point
interface and telecom applications:
Notes:
1. H = high level; L = low level; X = indeterminate
Block Diagram
– ATM
– SONET/SDH
– Switches
– Routers
5
4
1
2
A
B
Y
– Add-Drop Multiplexers
Z
High-Speed Differential Cable Repeater Application
Pin Configuration
Any LVDS R
R = Z
O
T
LVDS Repeater
X
R
= Z
O
T
VDD
A
B
6
5
4
1
2
3
Z
Z
O
T
O
X
Y
Z
GND
PS8660A
07/07/04
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