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PI6C49S1504LIE PDF预览

PI6C49S1504LIE

更新时间: 2024-10-01 01:19:43
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管
页数 文件大小 规格书
10页 1189K
描述
High Performance Selectable 1:4 Differential Fanout Buffer

PI6C49S1504LIE 技术参数

是否Rohs认证: 符合生命周期:Transferred
Reach Compliance Code:compliant风险等级:5.79
JESD-30 代码:R-PDSO-G28端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:2.5/3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:70 mA表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL

PI6C49S1504LIE 数据手册

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PI6C49S1504  
High Performance Selectable 1:4 Differential Fanout Buffer  
Features  
Description  
Î4 differential outputs with 2 banks  
e PI6C49S1504 is a high performance fanout buffer device-  
which supports up to 1.5GHz frequency. e device also uses  
Pericom's proprietary input detection technique to make sure  
illegal input conditions will be detected and reflected by output  
states. is device is ideal for systems that need to distribute low  
jitter clock signals to multiple destinations.  
ÎUser configurable output signaling standard for each bank:  
LVDS or LVPECL or HCSL  
ÎLVCMOS reference output up to 200MHz  
ÎUp to 1.5GHz output frequency for differential outputs  
ÎUltra low additive phase jitter: < 0.03 ps (typ) (differential  
156.25MHz, 12KHz to 20MHz integration range)  
Applications  
ÎNetworking systems including switches and Routers  
ÎSelectable reference inputs support either single-ended  
or differential or Xtal  
ÎHigh frequency backplane based computing and telecom  
ÎLow skew between outputs within banks (<40ps)  
ÎLow delay from input to output (Tpd typ. < 1.5ns)  
ÎSeparate Input output supply voltage for level shiꢀing  
Î2.5V / 3.3V power supply  
platforms  
ÎIndustrial temperature support  
ÎTSSOP-28 package  
Block Diagram  
Pin Configuration (28-Pin TSSOP)  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VEE/GND  
NC  
1
QA0  
nQA0  
2
OPMODEA[1:0]  
CLK_SEL0  
3
VDDO  
QA[0:1]  
2
CLK_SEL1  
CLK0  
4
OpModeA0  
OpModeA1  
QA1  
X1  
OSC  
X2  
5
OPMODEB[1:0]  
CLK0  
nCLK0  
CLK1  
6
nCLK0  
QB[0:1]  
2
7
nQA1  
CLK1  
nCLK1  
Ref_out  
nCLK1  
Xtal_In  
Xtal_Out  
Sync_OE  
IREF  
8
Ref_Out  
QB0  
9
CLK_SEL[1:0]  
nQB0  
10  
11  
12  
13  
14  
Sync_OE  
Iref  
Sync  
OpModeB1  
OpModeB0  
VDDO  
VDD  
QB1  
nQB1  
PI6C49S1504  
RevA  
04/01/13  
1
13-0025  

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