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PI6C49S1510AZDIEX PDF预览

PI6C49S1510AZDIEX

更新时间: 2024-09-30 14:35:15
品牌 Logo 应用领域
美台 - DIODES 驱动逻辑集成电路
页数 文件大小 规格书
19页 1777K
描述
Low Skew Clock Driver,

PI6C49S1510AZDIEX 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TQFN-48Reach Compliance Code:compliant
Factory Lead Time:21 weeks风险等级:1.72
Is Samacsys:N其他特性:IT ALSO OPERATES AT 3.3V NOMINAL
系列:6C输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N48长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Same Edge Skew-Max(tskwd):0.04 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:7 mm最小 fmax:1500 MHz
Base Number Matches:1

PI6C49S1510AZDIEX 数据手册

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A product Line of  
Diodes Incorporated  
PI6C49S1510A  
High Performance Differential Fanout Buffer  
Features  
Description  
Î10 differential outputs with 2 banks  
e PI6C49S1510A is a high performance fanout buffer device-  
which supports up to 1.5GHz frequency. It also integrates a  
unique feature with user configurable output signaling standards  
on per bank basis which provide great flexibilities to users. e  
device also uses Pericom's proprietary input detection technique  
to make sure illegal input conditions will be detected and re-  
flected by output states. is device is ideal for systems that need  
to distribute low jitter clock signals to multiple destinations.  
ÎUser configurable output signaling standard for each bank:  
LVDS or LVPECL or HCSL  
ÎLVCMOS reference output up to 200MHz  
ÎUp to 1.5GHz output frequency for differential outputs  
ÎUltra low additive phase jitter: < 0.02 ps (typ) (differential  
156.25MHz, 12KHz to 20MHz integration range); < 0.01 ps  
(typ) (differential 156.25MHz, 10kHz to 1MHz integration  
range)  
Applications  
ÎNetworking systems including switches and Routers  
ÎSelectable reference inputs support either single-ended  
or differential or Xtal  
ÎHigh frequency backplane based computing and telecom  
ÎLow skew between outputs within banks (<40ps)  
ÎLow delay from input to output (Tpd typ. < 0.9ns)  
ÎSeparate Input output supply voltage for level shiꢀing  
Î2.5V / 3.3V power supply  
platforms  
ÎIndustrial temperature support  
ÎTQFN-48 package  
Pin Configuration (48-TQFN)  
Block Diagram  
OPMODEA[1:0]  
48 47 46 45 44 43 42 41 40 39 38 37  
1
QA[0:4]  
QAO+  
QAO-  
QA1+  
QA1-  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QBO+  
QBO-  
QB1+  
QB1-  
5
2
3
X1  
OSC  
X2  
4
OPMODEB[1:0]  
IN0+  
IN0-  
5
V
V
DDO  
DDO  
QB[0:4]  
5
6
QA2+  
QA2-  
QB2+  
QB2-  
IN1+  
IN1-  
7
Ref_Out  
8
V
V
DDO  
DDO  
9
QA3+  
QA3-  
QA4+  
QA4-  
QB3+  
QB3-  
QB4+  
QB4-  
IN_SEL[1:0]  
10  
11  
12  
Sync_OE  
Iref  
Sync  
13 14 15 16 17 18 19 20 21 22 23 24  
www.diodes.com  
January 2018  
© Diodes Incorporated  
PI6C49S1510A  
Document Number DS40482 Rev 2-2  
1

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