捷配首页

Datasheet > 逻辑 > 延迟线> PDU18F-2MC5
PDU18F-2MC5 PDF预览

PDU18F-2MC5

更新时间： 2025-08-31 10:14:51
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路
页数 文件大小 规格书
5页 293K
描述
8-BIT PROGRAMMABLE DELAY LINE

阅读下载

中文翻译

获取价格

PDU18F-2MC5 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：SOP,
Reach Compliance Code：compliant风险等级：5.22
Is Samacsys：NJESD-30 代码：R-XDSO-G40
JESD-609代码：e3长度：52.832 mm
逻辑集成电路类型：ACTIVE DELAY LINE功能数量：1
抽头/阶步数：255端子数量：40
输出极性：COMPLEMENTARY封装主体材料：UNSPECIFIED
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
可编程延迟线：YES认证状态：Not Qualified
座面最大高度：7.112 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES端子面层：Tin (Sn)
端子形式：GULL WING端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：510 nsBase Number Matches：1

PDU18F-2MC5 数据手册

 浏览型号PDU18F-2MC5的Datasheet PDF文件第2页浏览型号PDU18F-2MC5的Datasheet PDF文件第3页浏览型号PDU18F-2MC5的Datasheet PDF文件第4页浏览型号PDU18F-2MC5的Datasheet PDF文件第5页 
PDU18F  
8-BIT PROGRAMMABLE  
DELAY LINE  
(SERIES PDU18F)  
FEATURES  
PACKAGES  
N/C  
OUT/  
OUT  
EN/  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
VCC  
N/C  
A0  
A1  
A2  
VCC  
N/C  
A3  
A4  
A5  
VCC  
N/C  
N/C  
N/C  
N/C  
VCC  
N/C  
A6  
1
2
3
4
5
6
7
8
•
•
•
•
•
•
•
•
Digitally programmable in 256 delay steps  
Monotonic delay-versus-address variation  
Two separate outputs: inverting & non-inverting  
Precise and stable delays  
PDU18F-xx  
DIP  
GND  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
EN/  
PDU18F-xxC5  
Input & outputs fully TTL interfaced & buffered  
Gull-Wing  
10 T2L fan-out capability  
Fits standard 40-pin DIP socket  
Auto-insertable  
9
PDU18F-xxM  
Military DIP  
PDU18F-xxMC5  
Military Gull-Wing  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A7  
IN  
N/C  
GND  
N/C  
N/C  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PDU18F-series device is a 8-bit digitally programmable delay line.  
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)  
IN  
Delay Line Input  
OUT Non-inverted Output  
OUT/ Inverted Output  
A0-A7 Address Bits  
EN/ Output Enable  
VCC +5 Volts  
depends on the address code (A7-A0) according to the following formula:  
TDA = TD0 + TINC * A  
where A is the address code, TINC is the incremental delay of the device,  
and TD0 is the inherent delay of the device. The incremental delay is  
GND Ground  
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The  
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state  
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into  
LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal  
operation.  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Incremental  
Total Delay  
•
•
•
Programmed delay tolerance: 5% or 2ns,  
Number  
Delay  
Change (ns)  
whichever is greater  
Per Step (ns)  
.5 ± .3  
Inherent delay (TD0): 13ns typical (OUT)  
12ns typical (OUT/)  
PDU18F-.5  
PDU18F-1  
PDU18F-2  
PDU18F-3  
PDU18F-4  
PDU18F-5  
PDU18F-6  
PDU18F-8  
PDU18F-10  
127.5 ± 6.4  
255 ± 12.8  
510 ± 25.5  
765 ± 38.3  
1,020 ± 51.0  
1,275 ± 63.8  
1,530 ± 76.5  
2,040 ± 102.0  
2,550 ± 127.5  
1 ± .5  
Setup time and propagation delay:  
Address to input setup (TAIS): 10ns  
Disable to output delay (TDISO): 6ns typ. (OUT)  
Operating temperature: 0° to 70° C  
Temperature coefficient: 100PPM/°C (excludes TD0)  
Supply voltage VCC: 5VDC ± 5%  
2 ± .5  
3 ± 1.0  
4 ± 1.0  
5 ± 1.5  
•
•
•
•
6 ± 1.5  
8 ± 2.0  
10 ± 2.0  
Supply current:  
I
CCH = 65ma  
NOTE: Any dash number between .5 and 10 not  
ICCL = 128ma  
shown is also available.  
•
Minimum pulse width: 6% of total delay  
1997 Data Delay Devices  
Doc #97006  
1/30/06  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
12345

中文翻译

下载PDF

与PDU18F-2MC5相关器件

型号 品牌 获取价格 描述 数据表
PDU18F-3 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-3C5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-3M DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-3MC5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-4 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-4C5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-4M DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-4MC5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE
PDU18F-5C5 DATADELAY

获取价格

 		8-BIT PROGRAMMABLE DELAY LINE

与PDU18F-2MC5相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2025 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证