Datasheet > PDU15F-12B4

PDU15F-12B4

更新时间： 2024-09-30 23:27:15

品牌	Logo	应用领域
其他 - ETC		延迟线逻辑集成电路
页数	文件大小	规格书
5页	82K
描述
Delay Line

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中文翻译

获取价格

数据手册

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PDU15F-12B4 数据手册

PDU15F

5-BIT PROGRAMMABLE

DELAY LINE

(SERIES PDU15F)

data

delay

devices, inc.

FEATURES

PACKAGES

OUT/

OUT

EN/

VCC

Digitally programmable in 32 delay steps

Monotonic delay-versus-address variation

Two separate outputs: inverting & non-inverting

Precise and stable delays

PDU15F-xx

DIP

PDU15F-xxA4

Gull-Wing

PDU15F-xxB4

J-Lead

GND

N/C

Input & outputs fully TTL interfaced & buffered

VCC

N/C

VCC

10 T²L fan-out capability

Fits standard 24-pin DIP socket

Auto-insertable

N/C

GND

N/C

EN/

PDU15F-xxM

Military DIP

PDU15F-xxMC4

Military Gull-Wing

10 15

11 14

12 13

GND

N/C

PIN DESCRIPTIONS

FUNCTIONAL DESCRIPTION

Delay Line Input

The PDU15F-series device is a 5-bit digitally programmable delay line.

The delay, TD_A, from the input pin (IN) to the output pins (OUT, OUT/)

depends on the address code (A4-A0) according to the following formula:

OUT Non-inverted Output

OUT/ Inverted Output

A0-A4 Address Bits

EN/ Output Enable

VCC +5 Volts

TD_A= TD₀+ T_INC* A

GND Ground

where A is the address code, T_INCis the incremental delay of the device,

and TD₀is the inherent delay of the device. The incremental delay is

specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The

enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state

and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced

into LOW and HIGH states, respectively. The address is not latched and must remain asserted during

normal operation.

DASH NUMBER SPECIFICATIONS

SERIES SPECIFICATIONS

Part

Number

Incremental Delay

Per Step (ns)

.5 ± .3

Total Delay

Change (ns)

15.5 ± 1.0

31 ± 1.6

62 ± 3.1

93 ± 4.7

124 ± 6.2

155 ± 7.8

186 ± 9.3

248 ± 12.4

310 ± 15.5

372 ± 18.6

465 ± 23.3

620 ± 31.0

Total programmed delay tolerance: 5% or 1ns,

whichever is greater

Inherent delay (TD₀): 9ns typical (OUT)

8ns typical (OUT/)

Setup time and propagation delay:

Address to input setup (T_AIS): 5ns

Disable to output delay (T_DISO): 6ns typ. (OUT)

Operating temperature: 0° to 70° C

Temperature coefficient: 100PPM/°C (excludes TD₀)

Supply voltage V_CC: 5VDC ± 5%

Supply current: I_CCH= 74ma

PDU15F-.5

PDU15F-1

PDU15F-2

PDU15F-3

PDU15F-4

PDU15F-5

PDU15F-6

PDU15F-8

PDU15F-10

PDU15F-12

PDU15F-15

PDU15F-20

1 ± .5

2 ± .5

3 ± 1.0

4 ± 1.0

5 ± 1.0

6 ± 1.0

8 ± 1.0

10 ± 1.5

12 ± 1.5

15 ± 1.5

20 ± 2.0

I_CCL= 30ma

Minimum pulse width: 10% of total delay

NOTE: Any dash number between .5 and 20 not

shown is also available.

Ó1997 Data Delay Devices

Doc #97003

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

1/13/97

12 3 4 5

中文翻译

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与PDU15F-12B4相关器件

型号	品牌	获取价格	描述	数据表
PDU15F-12M	ETC	获取价格	Delay Line
PDU-15F-12MC4	DATADELAY	获取价格	Active Delay Line, Programmable, 1-Func, 31-Tap, Complementary Output, TTL,
PDU15F-12MC4	ETC	获取价格	Delay Line
PDU-15F-12ME9	DATADELAY	获取价格	Active Delay Line, Programmable, 1-Func, 31-Tap, Complementary Output, TTL, LOW PROFILE, D
PDU15F-15	DATADELAY	获取价格	5-BIT PROGRAMMABLE DELAY LINE
PDU15F-15A4	ETC	获取价格	Delay Line
PDU15F-15B4	ETC	获取价格	Delay Line
PDU15F-15M	ETC	获取价格	Delay Line
PDU-15F-15MC4	DATADELAY	获取价格	Active Delay Line, Programmable, 1-Func, 31-Tap, Complementary Output, TTL,
PDU15F-15MC4	ETC	获取价格	Delay Line

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