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PDM41024LA10TA PDF预览

PDM41024LA10TA

更新时间: 2024-02-08 20:40:39
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
8页 295K
描述
1 Megabit Static RAM 128K x 8-Bit

PDM41024LA10TA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.91
Is Samacsys:N最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.0005 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.23 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

PDM41024LA10TA 数据手册

 浏览型号PDM41024LA10TA的Datasheet PDF文件第1页浏览型号PDM41024LA10TA的Datasheet PDF文件第3页浏览型号PDM41024LA10TA的Datasheet PDF文件第4页浏览型号PDM41024LA10TA的Datasheet PDF文件第5页浏览型号PDM41024LA10TA的Datasheet PDF文件第6页浏览型号PDM41024LA10TA的Datasheet PDF文件第7页 
PDM41024  
Pin Configuration  
SOJ  
TSOP (I)  
Vcc  
A15  
CE2  
WE  
A13  
A8  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
A11  
A9  
A8  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
Vss  
I/O2  
I/O1  
I/O0  
A0  
A13  
WE  
CE2  
A15  
Vcc  
NC  
A16  
A14  
A12  
A7  
28  
27  
26  
25  
24  
23  
A6  
A9  
A5  
9
A11  
OE  
A4  
10  
11  
12  
13  
14  
15  
16  
9
A3  
10  
11  
12  
13  
14  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A2  
A1  
22  
21  
20  
19  
18  
17  
A6  
A5  
A4  
A1  
A2  
A3  
A0  
I/O0  
I/O1  
I/O2  
Vss  
15  
16  
Pin Description  
Name  
Description  
Address Inputs  
(1)  
Truth Table  
A16-A0  
I/O7-I/O0  
OE  
OE  
WE  
CE1  
CE2  
I/O  
MODE  
Data Inputs/Outputs  
Output Enable Input  
Write Enable Input  
Chip Enable Inputs  
No Connect  
X
X
L
X
X
H
L
H
X
L
L
L
X
L
Hi-Z  
Hi-Z  
Standby  
Standby  
Read  
WE  
H
H
H
D
OUT  
CE1, CE2  
NC  
X
H
D
Write  
IN  
H
Hi-Z  
Output Disable  
V
Power (+5V)  
CC  
SS  
V
Ground  
NOTE: 1. H = V , L = V , X = DON’T CARE  
IH  
IL  
(1)  
Absolute Maximum Ratings  
Symbol  
Rating  
Com’l.  
Ind.  
Unit  
V
Terminal Voltage with Respect to V  
Temperature Under Bias  
Storage Temperature  
–0.5 to +7.0  
–55 to +125  
–55 to +125  
1.0  
–0.5 to +7.0  
–65 to +135  
–65 to +150  
1.0  
V
°C  
°C  
W
TERM  
BIAS  
STG  
SS  
T
T
P
Power Dissipation  
T
I
DC Output Current  
50  
50  
mA  
°C  
OUT  
(2)  
T
Maximum Junction Temperature  
125  
145  
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device.This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating con-  
ditions for extended periods may affect reliability.  
2. Appropriate thermal calculations should be performed in all cases and specifically for  
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-  
culation should be of the form: T = T + P * θ where T is the ambient temperature, P  
j
a
ja  
a
is average operating power and θ the thermal resistance of the package. For this  
ja  
product, use the following θ values:  
ja  
o
SOJ: 72 C/W  
o
TSOP: 95 C/W  
2
4/09/98 - Rev. 3.3  

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