Datasheet > PDM34078SA12QA

PDM34078SA12QA

更新时间： 2023-01-02 20:35:36

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
14页	318K
描述
SRAM

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数据手册

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PDM34078SA12QA 数据手册

PDM34078

Pinout

Name

I/O

Description

Name

I/O

Description

A14-A2

A1, A0

DQ1-DQ32

Address Inputs A14-A2

Address Inputs A1 & A0

Read/Write Data

CE, CE2, CE2

BWE

Chip Enables

Byte Write Enable

Byte Write Enables

Output Enable

Clock

I/O

BW1-BW4

—

No Connect

(1)

MODE

Burst Sequence Select

Burst Counter Advance

Controller Address Status

Processor Address Status

Global Write

CLK

ADV

Sleep Mode

ADSC

ADSP

—

Power Supply (+3.3V)

Output Power for DQ’s (+3.3V ±5%)

Array Ground

CCQ

(1)

Must be tied HIGH for

proper operation

Output Ground for DQ’s

SSQ

NOTE: 1.MODE and FT are DC operated pins. Do not alter input state while device is operating.

Burst Sequence Table

(1)

Interleaved

(2)

Linear

Mode = V

Burst Sequence

Mode = NC or

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A14-A2, A1, A0

A14-A2,0,0

A14-A2,0,1

A14-A2,1,0

A14-A2,1,1

A14-A2,0,1

A14-A2,1,0

A14-A2,1,1

A14-A2,0,0

A14-A2,1,0

A14-A2,1,1

A14-A2,0,0

A14-A2,0,1

A14-A2,1,1

A14-A2,0,0

A14-A2,0,1

A14-A2,1,0

Note: 1. Interleaved = x86 and Pentium.

2. Linear = 680x0 and Power PC compatible.

Partial Truth Table for Writes

Asynchronous Truth Table

Operation

OE I/O Status

GW BWE BW1 BW2 BW3 BW4

Function

Read

Data Out

READ

Read

High-Z

READ

Write

High-Z: Write Data In

High-Z

WRITE Byte 1

WRITE All Bytes

Deselected

Sleep

High-Z

NOTE: 1. L = Low, H = High, X = Don’t Care.

2. For a write operation following a read operation,

OE must be high before the input data required

setup time and held high through the input data

hold time.

NOTE: 1. L = Low, H = High, X = Don’t Care.

2. Using BWE and BW1 through BW4, any one or

more bytes may be written.

3. This device contains circuitry that will ensure

the outputs will be in high-Z during powerup.

Rev 1.0 - 5/01/98

1 2 345 6 7...14

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