PDM34078
Pinout
Name
I/O
Description
Name
I/O
Description
A14-A2
A1, A0
DQ1-DQ32
NC
I
Address Inputs A14-A2
Address Inputs A1 & A0
Read/Write Data
CE, CE2, CE2
BWE
I
I
Chip Enables
I
Byte Write Enable
Byte Write Enables
Output Enable
Clock
I/O
BW1-BW4
OE
I
—
No Connect
I
(1)
MODE
I
I
I
I
I
I
Burst Sequence Select
Burst Counter Advance
Controller Address Status
Processor Address Status
Global Write
CLK
I
ADV
ZZ
I
Sleep Mode
ADSC
ADSP
GW
V
V
V
V
—
—
—
—
Power Supply (+3.3V)
CC
Output Power for DQ’s (+3.3V ±5%)
Array Ground
CCQ
SS
(1)
FT
Must be tied HIGH for
proper operation
Output Ground for DQ’s
SSQ
NOTE: 1.MODE and FT are DC operated pins. Do not alter input state while device is operating.
Burst Sequence Table
(1)
Interleaved
(2)
Linear
Mode = V
Burst Sequence
Mode = NC or
SS
V
CC
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
Note: 1. Interleaved = x86 and Pentium.
2. Linear = 680x0 and Power PC compatible.
Partial Truth Table for Writes
Asynchronous Truth Table
Operation
ZZ
OE I/O Status
GW BWE BW1 BW2 BW3 BW4
Function
Read
L
L
L
L
H
L
H
X
X
X
Data Out
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
Read
High-Z
READ
Write
High-Z: Write Data In
High-Z
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
Deselected
Sleep
L
High-Z
X
X
X
X
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. For a write operation following a read operation,
OE must be high before the input data required
setup time and held high through the input data
hold time.
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. Using BWE and BW1 through BW4, any one or
more bytes may be written.
3. This device contains circuitry that will ensure
the outputs will be in high-Z during powerup.
4
Rev 1.0 - 5/01/98