Datasheet > PCX7457VG866NC

PCX7457VG866NC

更新时间： 2023-01-03 05:21:47

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
60页	917K
描述
RISC Microprocessor, 32-Bit, 866MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483

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PCX7457VG866NC 数据手册

– Memory programmable as write-back/write-through, caching-inhibited/caching-

allowed, and memory coherency enforced/memory coherency not enforced on a

page or block basis

– Separate IBATs and DBATs (eight each) also defined as SPRs

– Separate instruction and data translation lookaside buffers (TLBs)

Both TLBs are 128-entry, two-way set-associative, and use LRU replacement

algorithm

TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table

search is performed in hardware or by system software)

• Efficient data flow

– Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to

256 bits

– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs

– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1

cache

– As many as eight outstanding, out-of-order, cache misses are allowed between the

L1 data cache and L2/L3 bus

– As many as 16 out-of-order transactions can be present on the MPX bus

– Store merging for multiple store misses to the same line. Only coherency action

taken (address-only) for store misses merged to all 32 bytes of a cache block (no

data tenure needed)

– Three-entry finished store queue and five-entry completed store queue between the

LSU and the L1 data cache

– Separate additional queues for efficient buffering of outbound data (such as castouts

and write-through stores) from the L1 data cache and L2 cache

• Multiprocessing support features include the following:

– Hardware-enforced, MESI cache coherency protocols for data cache

– Load/store with reservation instruction pair for atomic memory references,

semaphores, and other multiprocessor operations

• Power and thermal management

– 1.6V processor core

– The following three power-saving modes are available to the system:

Nap—Instruction fetching is halted. Only those clocks for the time base,

decrementer, and JTAG logic remain running. The part goes into the doze state to

snoop memory operations on the bus and then back to nap using a QREQ/QACK

processor-system handshake protocol

Sleep—Power consumption is further reduced by disabling bus snooping, leaving

only the PLL in a locked and running state. All internal functional units are disabled

Deep sleep—When the part is in the sleep state, the system can disable the PLL.

The system can then disable the SYSCLK source for greater system power savings.

Power-on reset procedures for restarting and relocking the PLL must be followed on

exiting the deep sleep state

PC7457

5345D–HIREL–07/06

1...5 6 789 10 11...60

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与PCX7457VG866NC相关器件

型号	品牌	描述	获取价格	数据表
PCX7457VGH1000NC	ATMEL	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格
PCX7457VGH1050NC	ATMEL	RISC Microprocessor, 32-Bit, 1050MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格
PCX7457VGH1150NC	ATMEL	RISC Microprocessor, 32-Bit, 1150MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格
PCX7457VGH1200NC	ATMEL	RISC Microprocessor, 32-Bit, 1200MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格
PCX7457VGH1300NC	ATMEL	RISC Microprocessor, 32-Bit, 1300MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM P	获取价格
PCX7457VGH500NC	ATMEL	RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PI	获取价格

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