Datasheet > PCM56P-KG4

PCM56P-KG4

更新时间： 2024-01-20 20:56:14

品牌	Logo	应用领域
德州仪器 - TI		输入元件光电二极管转换器
页数	文件大小	规格书
16页	725K
描述
SERIAL INPUT LOADING, 1.5us SETTLING TIME, 16-BIT DAC, PDIP16, GREEN, PLASTIC, DIP-16

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技术参数
数据手册

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PCM56P-KG4 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP16,.3	针数：	16
Reach Compliance Code：	compliant	风险等级：	5.69
最大模拟输出电压：	3 V	最小模拟输出电压：	-3 V
转换器类型：	D/A CONVERTER	输入位码：	2'S COMPLEMENT BINARY
输入格式：	SERIAL	JESD-30 代码：	R-PDIP-T16
JESD-609代码：	e4	长度：	19.305 mm
标称负供电电压：	-5 V	位数：	16
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP16,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	+-5/+-12 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	标称安定时间 (tstl)：	1.5 µs
子类别：	Other Converters	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

PCM56P-KG4 数据手册

(1)

Clock

Data

MSB

LSB

(2)

MSB

Latch

Enable

(3)

(4)

NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data

word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch

enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going

negative.

FIGURE 7. Input Timing Diagram.

source and drain of the FET switch operate at a virtual

> 40ns

ground when “C” and “B” are connected in the sample

mode, there is no increase in distortion caused by the

modulation effect of R_ONby the audio signal.

Data

Input

LSB

MSB

Figure 10 shows the deglitcher controls for both left and

right channels which are produced by timing control logic.

A delay of 1.5µs (tω) is provided to allow the output of the

PCM56 to settle within a small error band around its final

value before connecting it to the channel output. Due to the

fast settling time of the PCM56 it is possible to minimize the

delay between the left- and right-channel outputs when

using a single D/A converter for both channels. This is

important because the right- and left-channel data are recorded

in-phase and the use of the slower D/A converter would

result in significant phase error at higher frequencies.

>15ns >15ns

Clock

Input

> 40ns

> 5ns

> 100ns

Latch

Enable

> 15ns

> One Clock Cycle

The obvious solution to the phase shift problem in a two-

channel system would be to use two D/A converters (one per

channel) and time the outputs to change simultaneously.

Figure 11 shows a block diagram of the final test circuitry

used for PCM56. It should be noted that no deglitching

circuitry is required on the DAC output to meet specified

THD performance. This means that when one PCM56 is

used per channel, the need for all the sample/hold and

controls circuitry associated with a single DAC (two-channel)

design is effectively eliminated. The PCM56 is tested to

meet its THD specifications without the need for output

deglitching.

FIGURE 8. Input Timing Relationships.

of RF radiation or pickup is loop area; therefore, signal leads

and their return conductors should be kept close together.

This reduces the external magnetic field along with any

radiation. Also, if a signal lead and its return conductor are

wired close together, they represent a small flux-capture

cross section for any external field. This reduces radiation

pickup in the circuit.

APPLICATIONS

A low-pass filter is required after the PCM56 to remove all

unwanted frequency components caused by the sampling

frequency as well as those resulting from the discrete nature

of the D/A output. This filter must have a flat frequency

response over the entire audio band (0-20kHz) and a very

high attenuation above 20kHz.

Figures 9 and 10 show a circuit and timing diagram for a

single PCM56 used to obtain both left- and right-channel

output in a typical digital audio system. The audio output of

the PCM56 is alternately time-shared between the left and

right channels. The design is greatly simplified because the

PCM56 is a complete D/A converter requiring no external

reference or output op amp.

Most previous digital audio circuits used a higher order (9-

13 pole) analog filter. However, the phase response of an

analog filter with these amplitude characteristics is nonlinear

and can disturb the pulse-shaped characteristic transients

contained in music.

A sample/hold (S/H) amplifier, or “deglitcher” is required at

the output of the D/A for both the left and right channel, as

shown in Figure 9. The S/H amplifier for the left channel is

composed of A₁, SW₁, and associated circuitry. A₁is used

as an integrator to hold the analog voltage in C₁. Since the

PCM56

1...4 5 678 9 10...16

中文翻译

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与PCM56P-KG4相关器件

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PCM56P-L	BB	Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER	获取价格
PCM56P-LG4	TI	SERIAL INPUT LOADING, 1.5us SETTLING TIME, 16-BIT DAC, PDIP16, GREEN, PLASTIC, DIP-16	获取价格
PCM56U	BB	Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER	获取价格
PCM56UG4	TI	Series Input 16-Bit Monolithic Digital-to-Analog Converter 16-SOIC	获取价格
PCM-5825	ETC	NS Geode SBC with CPU, 4 COMs, Audio, VGA/LCD and Ethernet	获取价格
PCM-5825-G0A2	ETC	NS Geode SBC with CPU, 4 COMs, Audio, VGA/LCD and Ethernet	获取价格

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