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PCM55JP PDF预览

PCM55JP

更新时间: 2024-01-11 23:17:31
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管转换器
页数 文件大小 规格书
9页 88K
描述
PARALLEL, WORD INPUT LOADING, 3us SETTLING TIME, 16-BIT DAC, PDSO24, MINI, PLASTIC, SOIC-24

PCM55JP 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOIC-24
针数:24Reach Compliance Code:compliant
ECCN代码:3A001.A.5.BHTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
最大模拟输出电压:3 V最小模拟输出电压:-3 V
转换器类型:D/A CONVERTER输入位码:COMPLEMENTARY BINARY, COMPLEMENTARY 2'S COMPLEMENT, COMPLEMENTARY OFFSET BINARY
输入格式:PARALLEL, WORDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:15.5 mm
湿度敏感等级:1标称负供电电压:-5 V
位数:16功能数量:1
端子数量:24最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.5
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):235电源:+-5 V
认证状态:Not Qualified座面最大高度:2.5 mm
标称安定时间 (tstl):3 µs子类别:Other Converters
最大压摆率:45 mA标称供电电压:5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.4 mm
Base Number Matches:1

PCM55JP 数据手册

 浏览型号PCM55JP的Datasheet PDF文件第3页浏览型号PCM55JP的Datasheet PDF文件第4页浏览型号PCM55JP的Datasheet PDF文件第5页浏览型号PCM55JP的Datasheet PDF文件第7页浏览型号PCM55JP的Datasheet PDF文件第8页浏览型号PCM55JP的Datasheet PDF文件第9页 
error at each sampling point. The THD can then be ex-  
pressed as:  
INSTALLATION AND OPERATING  
INSTRUCTIONS  
(2)  
POWER SUPPLY CONNECTIONS  
1
n
[ΕL (i) + ΕQ (i)]2  
For optimum performance and noise rejection, power supply  
decoupling capacitors should be added as shown in the  
connections diagram. These capacitors (1µF tantalum or  
electrolytic recommended) should be located close to the  
converter.  
Σ
n
εrms  
i = 1  
THD =  
=
100%  
Εrms  
Εrms  
where Erms is the rms signal voltage level.  
This expression indicates that, in general, there is a correla-  
tion between the THD and the square root of the sum of the  
squares of the linearity errors at each digital word of interest.  
However, this expression does not mean that the worst-case  
linearity error of the D/A is directly correlated to the THD.  
MSB ERROR ADJUSTMENT PROCEDURE  
(OPTIONAL)  
The MSB error of the PCM54 and PCM55 can be adjusted  
to make the differential linearity error (DLE) at BPZ essen-  
tially zero. This is important when the signal output levels  
are very low because zero crossing noise (DLE at BPZ)  
becomes very significant when compared to the small code  
changes occurring in the LSB portion of the converter.  
For PCM54/55 the test period was chosen to be 22.7µs  
(44.1kHz) which is compatible with the EIAJ STC-007  
specification for PCM audio. The test frequency is 420Hz  
and the amplitude of the input signal is 0dB, –20dB, and  
–60dB down from full scale.  
Differential linearity error at bipolar zero is guaranteed to  
meet data sheet specifications without any external adjust-  
ment. However, a provision has been made for an optional  
adjustment of the MSB linearity point which makes it  
possible to eliminate DLE error at BPZ (PCM54 only). Two  
procedures are given to allow either static or dynamic  
adjustment. The dynamic procedure is preferred because of  
the difficulty associated with the static method (accurately  
measuring 16-bit LSB steps).  
Figure 4 shows the typical THD as a function of output  
voltage.  
Figure 5 shows typical THD as a function of frequency.  
10.0  
4.0  
2.0  
1.0  
To statically adjust DLE at BPZ, refer to the circuit shown  
in Figure 6 or the PCM54 connection diagram. After allow-  
ing ample warm-up time (20-30 minutes) to assure stable  
operation of the PCM54, select input code 8000 hexadeci-  
mal (all bits off except the MSB). Measure and record it.  
Change the digital input code to 7FFF hexadecimal (all bits  
off except the MSB). Adjust the 100kpotentiometer to  
make the audio output read 92µV more than the voltage  
reading of the previous code (a ILSB step = 92µV).  
0.4  
0.2  
0.1  
14 Bits  
0.04  
0.02  
0.01  
0.004  
0.002  
0.001  
16 Bits  
–20  
–60  
–50  
–40  
–30  
–10  
0
A much simpler method is to dynamically adjust the DLE at  
BPZ. Again, refer to Figure 6 or the PCM54 connection  
diagram for circuitry and component values. Assuming the  
device has been installed in a digital audio application  
circuit, send the appropriate digital input to produce a –60dB  
level sinusoidal output. While measuring the THD of the  
audio circuit output, adjust the 100kpotentiometer until a  
minimum level of distortion is observed.  
VOUT (dB)  
0dB = Full-Scale Range (FSR)  
FIGURE 4. Total Harmonic Distortion (THD) vs VOUT  
.
0.1  
0.05  
0.02  
560kΩ  
1MΩ  
100kΩ  
330kΩ  
0.01  
1
–20dB  
–VCC  
0.005  
27  
0.002  
Full Scale  
0.001  
100  
1k  
10k 20k  
FIGURE 6. MSB Differential Linearity at Bipolar Zero Ad-  
justment Circuit (optional).  
Frequency (Hz)  
FIGURE 5. Total Harmonic Distortion (THD) vs  
Frequency.  
®
6
PCM54/55  

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