PCM3070
SLAS724 –FEBRUARY 2011
www.ti.com
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 2.2
–0.3 to 2.2
–0.3 to 3.9
–0.3 to 3.9
to IOVDD + 0.3
to AVdd + 0.3
–40 to 85
UNIT
V
AVdd to AVss
DVdd to DVss
V
IOVDD to IOVSS
V
LDOIN to AVss
V
Digital Input voltage
Analog input voltage
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
V
V
°C
°C
°C
W
105
(TJ Max – TA)/ θJA
35
QFN package (RHB)
Power dissipation
θJA Thermal impedance
C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
MAX UNIT
LDOIN
AVdd
Power Supply Voltage Range
Referenced to AVss(1)
1.9
V
1.95
1.5
1.5
1.8
1.8
IOVDD
DVdd(2)
Referenced to IOVSS(1)
Referenced to DVss(1)
3.6
1.95
PLL Input Frequency
Clock divider uses fractional divide
(D > 0), P=1, DVdd ≥ 1.65V
10
20
MHz
MHz
MHz
Clock divider uses integer divide
(D = 0), P=1, DVdd ≥ 1.65V
0.512
20
MCLK
Master Clock Frequency
MCLK; Master Clock Frequency; DVdd ≥ 1.65V
MCLK; Master Clock Frequency; DVdd ≥ 1.26V
50
25
SCL
SCL Clock Frequency
400
kHz
pF
CLout
TOPR
Digital output load capacitance
Operating Temperature Range
10
–40
85
°C
(1) All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground
signals.
(2) At DVdd values lower than 1.65V, the PLL does not function. Please see the Maximum PCM3070 Clock Frequencies table in the
PCM3070 Application Reference Guide (SLAU332) for details on maximum clock frequencies.
6
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): PCM3070