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PCD5094 PDF预览

PCD5094

更新时间: 2024-01-12 04:31:46
品牌 Logo 应用领域
恩智浦 - NXP 控制器
页数 文件大小 规格书
16页 87K
描述
DECT baseband controller

PCD5094 技术参数

生命周期:ObsoleteReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PQFP-G100长度:20 mm
功能数量:1端子数量:100
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.7X.9封装形状:RECTANGULAR
封装形式:FLATPACK电源:3/3.3,5 V
认证状态:Not Qualified座面最大高度:3.2 mm
子类别:Other Telecom ICs表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

PCD5094 数据手册

 浏览型号PCD5094的Datasheet PDF文件第4页浏览型号PCD5094的Datasheet PDF文件第5页浏览型号PCD5094的Datasheet PDF文件第6页浏览型号PCD5094的Datasheet PDF文件第8页浏览型号PCD5094的Datasheet PDF文件第9页浏览型号PCD5094的Datasheet PDF文件第10页 
Philips Semiconductors  
Objective specification  
DECT baseband controller  
PCD5094  
STATE  
SYMBOL  
LIFM  
PIN  
I/O  
AFTER  
RESET  
PIN TYPE  
PIN DESCRIPTION  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
I
0.7 V  
ANAIOD1  
ANAIOD1  
supply  
negative input from line interface  
positive input from line interface  
LIFP  
I
0.7 V  
VSSA  
negative supply voltage for analog circuits  
negative input from microphone  
positive input from microphone  
positive microphone supply voltage (+2 V)  
reference voltage (+2 V)  
MICM  
MICP  
VMIC  
Vref  
I
0.7 V  
ANAIOR1  
ANAIOR1  
ANAIOD1  
ANAIOD1  
ANAIOR1  
supply  
I
0.7 V  
O
off  
O
2.0 V  
VBGP  
VDDA  
O
1.25 V  
bandgap output voltage (+1.25 V)  
positive supply voltage for analog circuits  
negative output to earpiece  
EARM  
EARP  
EN_WATCHDOG  
P1.0  
O
1.4 V  
1.4 V  
ANAIOD1  
ANAIOD1  
O
positive output to earpiece  
I
DIUP0PES watchdog enable input  
I/O  
I/O  
I/O  
O
H
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISP2DPES general purpose 6.912 MHz output  
ISP2DPES data after clock recovery network  
ISP2DPES R_DATA comparator output  
P1.1  
H
P1.2  
H
GP_CLK7  
DPLL_DATA  
R_SLICED  
VDD5V_1  
P1.3  
L
O
L
O
L
supply  
positive supply voltage 1 for the +5 V interface  
I/O  
I/O  
I/O  
I/O  
I/O  
H
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
P1.4  
H
P1.5  
H
P1.6  
off  
off  
ISI8DPES  
ISI8DPES  
supply  
bidirectional 80C51 port pin  
bidirectional 80C51 port pin  
positive supply voltage 2 (+3 V)  
negative buzzer output  
P1.7  
VDD3V_2  
BZM  
O
L
ANAIOD2  
ANAIOD2  
supply  
BZP  
O
L
positive buzzer output  
VSS2  
negative supply voltage 2  
negative supply voltage 3  
VSS3  
supply  
P3.0  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
H
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
ISQ2CPES bidirectional 80C51 port pin  
P3.1  
H
P3.2  
H
P3.3  
H
P3.4  
H
P3.5  
H
P3.6  
H
P3.7  
H
P2.0  
H
P2.1  
H
1997 Jul 21  
7

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