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PCA9554ABS3 PDF预览

PCA9554ABS3

更新时间: 2024-01-06 01:35:11
品牌 Logo 应用领域
恩智浦 - NXP 并行IO端口微控制器和处理器外围集成电路
页数 文件大小 规格书
30页 179K
描述
8-bit I2C-bus and SMBus I/O port with interrupt

PCA9554ABS3 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:QFN包装说明:HVQFN-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.12Is Samacsys:N
JESD-30 代码:S-PQCC-N16JESD-609代码:e4
长度:3 mm湿度敏感等级:1
位数:8I/O 线路数量:8
端口数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC16,.12SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Parallel IO Port
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9554ABS3 数据手册

 浏览型号PCA9554ABS3的Datasheet PDF文件第4页浏览型号PCA9554ABS3的Datasheet PDF文件第5页浏览型号PCA9554ABS3的Datasheet PDF文件第6页浏览型号PCA9554ABS3的Datasheet PDF文件第8页浏览型号PCA9554ABS3的Datasheet PDF文件第9页浏览型号PCA9554ABS3的Datasheet PDF文件第10页 
PCA9554/PCA9554A  
NXP Semiconductors  
8-bit I2C-bus and SMBus I/O port with interrupt  
6.1.2 Register 0 - Input Port register  
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless  
of whether the pin is defined as an input or an output by Register 3. Writes to this register  
have no effect.  
The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no  
external signal externally applied because of the internal pull-up resistors.  
Table 4.  
Register 0 - Input Port register bit description  
Bit  
7
Symbol  
Access  
Value  
Description  
I7  
I6  
I5  
I4  
I3  
I2  
I1  
I0  
read only  
read only  
read only  
read only  
read only  
read only  
read only  
read only  
X
X
X
X
X
X
X
X
determined by externally applied logic level  
6
5
4
3
2
1
0
6.1.3 Register 1 - Output Port register  
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.  
Bit values in this register have no effect on pins defined as inputs. Reads from this register  
return the value that is in the flip-flop controlling the output selection, not the actual pin  
value.  
Table 5.  
Register 1 - Output Port register bit description  
Legend: * default value.  
Bit  
7
Symbol  
O7  
Access  
Value  
1*  
Description  
R
R
R
R
R
R
R
R
reflects outgoing logic levels of pins defined as  
outputs by Register 3  
6
O6  
1*  
5
O5  
1*  
4
O4  
1*  
3
O3  
1*  
2
O2  
1*  
1
O1  
1*  
0
O0  
1*  
PCA9554_9554A_7  
© NXP B.V. 2006. All rights reserved.  
Product data sheet  
Rev. 07 — 13 November 2006  
7 of 30  

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