Datasheet > PCA9551PW,112

PCA9551PW,112

更新时间： 2024-02-26 17:14:59

品牌	Logo	应用领域
恩智浦 - NXP		PC 驱动光电二极管接口集成电路
页数	文件大小	规格书
26页	169K
描述
PCA9551 - 8-bit I2C-bus LED driver with programmable blink rates TSSOP 16-Pin

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PCA9551PW,112 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP, TSSOP16,.25
针数：	16	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.12
数据输入模式：	SERIAL	接口集成电路类型：	LED DISPLAY DRIVER
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	5 mm	湿度敏感等级：	1
复用显示功能：	NO	功能数量：	1
区段数：	8	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	1.1 mm	子类别：	Display Drivers
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	最小 fmax：	0.4 MHz
Base Number Matches：	1

PCA9551PW,112 数据手册

PCA9551

NXP Semiconductors

8-bit I²C-bus LED driver with programmable blink rates

Table 2.

Symbol Pin

SO16, TSSOP16 HVQFN16

Pin description …continued

Description

LED7

RESET

SCL

LED driver 7

reset input (active LOW)

serial clock line

serial data line

SDA

V_DD

supply voltage

[1] HVQFN16 package die supply ground is connected to both V_SSpin and exposed center pad. V_SSpin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

6. Functional description

Refer to Figure 1 “Block diagram of PCA9551”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9551 is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

slave address

A2 A1 A0 R/W

fixed

hardware

selectable

002aac505

Fig 5. PCA9551 slave address

The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9551, which will be stored in the Control register.

B2 B1 B0

002aac506

Auto-Increment flag

Reset state: 00h

Fig 6. Control register

The lowest 3 bits are used as a pointer to determine which register will be accessed.

PCA9551_8

Product data sheet

Rev. 08 — 31 July 2008

4 of 26

1 2 345 6 7...26

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