Datasheet > PCA9537DP.118

PCA9537DP.118

更新时间： 2022-03-03 22:52:17

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
24页	136K
描述
4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

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PCA9537DP.118 数据手册

PCA9537

NXP Semiconductors

4-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6. Functional description

Refer to Figure 1 “Block diagram of PCA9537”.

6.1 Device address

slave address

R/W

fixed

002aae635

Fig 3. PCA9537 address

6.2 Registers

6.2.1 Command byte

The command byte is the ﬁrst byte to follow the address byte during a write transmission.

It is used as a pointer to determine which of the registers will be written or read.

Table 3.

Command byte

Protocol

Command

Function

read byte

Input Port register

Output Port register

Polarity Inversion register

Conﬁguration register

read/write byte

6.2.2 Register 0 - Input Port register

This register is a read-only port. It reﬂects the incoming logic levels of the pins, regardless

of whether the pin is deﬁned as an input or an output by Register 3. Writes to this register

have no effect.

The default value ‘X’ is determined by the externally applied logic level.

Table 4.

Legend: * default value.

Bit

Symbol

Access

Value

Description

read only

not used

value ‘X’ is determined by externally applied logic

level

PCA9537_5

Product data sheet

Rev. 05 — 7 May 2009

4 of 24

1 2 345 6 7...24

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