Datasheet > 微控制器和处理器 > 并行 IO 端口> PCA9536DR

PCA9536DR

更新时间： 2024-01-09 17:26:24

品牌	Logo	应用领域
德州仪器 - TI		并行IO端口微控制器和处理器外围集成电路光电二极管 PC 时钟
页数	文件大小	规格书
25页	476K
描述
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS

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PCA9536DR 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	VFBGA, BGA8,2X4,20	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.71
JESD-30 代码：	R-XBGA-B8	JESD-609代码：	e1
长度：	1.98 mm	湿度敏感等级：	1
位数：	4	I/O 线路数量：	4
端口数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	VFBGA
封装等效代码：	BGA8,2X4,20	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	0.5 mm	子类别：	Parallel IO Ports
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	0.9 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

PCA9536DR 数据手册

PCA9536

REMOTE 4-BIT I²C AND SMBus I/O EXPANDER

WITH CONFIGURATION REGISTERS

www.ti.com

SCPS125C–APRIL 2006–REVISED NOVEMBER 2006

I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak

pullup (100 kΩ typ) to V_CC. The input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

this case, there are low-impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address

byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 2).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

Start Condition

Stop Condition

Figure 1. Definition of Start and Stop Conditions

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