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PCA9536DR PDF预览

PCA9536DR

更新时间: 2024-02-23 18:56:17
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路光电二极管PC时钟
页数 文件大小 规格书
25页 476K
描述
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS

PCA9536DR 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA, BGA8,2X4,20针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
JESD-30 代码:R-XBGA-B8JESD-609代码:e1
长度:1.98 mm湿度敏感等级:1
位数:4I/O 线路数量:4
端口数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:VFBGA
封装等效代码:BGA8,2X4,20封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:0.5 mm子类别:Parallel IO Ports
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.9 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9536DR 数据手册

 浏览型号PCA9536DR的Datasheet PDF文件第3页浏览型号PCA9536DR的Datasheet PDF文件第4页浏览型号PCA9536DR的Datasheet PDF文件第5页浏览型号PCA9536DR的Datasheet PDF文件第7页浏览型号PCA9536DR的Datasheet PDF文件第8页浏览型号PCA9536DR的Datasheet PDF文件第9页 
PCA9536  
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER  
WITH CONFIGURATION REGISTERS  
www.ti.com  
SCPS125CAPRIL 2006REVISED NOVEMBER 2006  
The slave address equates to 65 (decimal) and 41 (hexadecimal).  
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read  
is selected, while a low (0) selects a write operation.  
Control Register and Command Byte  
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is  
stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and  
the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be  
written or read through the I2C bus. The command byte is sent only during a write transmission.  
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until  
a new command byte has been sent.  
0
0
0
0
0
0
B1 B0  
Figure 5. Control Register Bits  
Command Byte  
CONTROL REGISTER BITS  
COMMAND BYTE  
(HEX)  
POWER-UP  
DEFAULT  
REGISTER  
PROTOCOL  
B1  
0
B0  
0
0x00  
0x01  
0x02  
0x03  
Input Port  
Output Port  
Read byte  
1111 XXXX  
1111 1111  
0000 0000  
1111 1111  
0
1
Read/write byte  
Read/write byte  
Read/write byte  
1
0
Polarity Inversion  
Configuration  
1
1
6
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