Datasheet > PALCE16V8Q-10PI

PALCE16V8Q-10PI

更新时间： 2024-01-28 06:41:35

品牌	Logo	应用领域
超微 - AMD		/
页数	文件大小	规格书
26页	221K
描述
EE CMOS 20-Pin Universal Programmable Array Logic

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中文翻译

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技术参数
数据手册

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PALCE16V8Q-10PI 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.64	Is Samacsys：	N
最大时钟频率：	71.4 MHz	JESD-30 代码：	R-PDIP-T20
专用输入次数：	10	I/O 线路数量：	8
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		组织：	10 DEDICATED INPUTS, 8 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	IN-LINE
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	THROUGH-HOLE
端子位置：	DUAL	Base Number Matches：	1

PALCE16V8Q-10PI 数据手册

AMD

Power-Up Reset

Programming and Erasing

All flip-flops power up to a logic LOW for predictable sys-

tem initialization. Outputs of the PALCE16V8 will de-

pend on whether they are selected as registered or

combinatorial. If registered is selected, the output will be

HIGH. If combinatorial is selected, the output will be a

function of the logic.

The PALCE16V8 can be programmed on standard logic

programmers. It also may be erased to reset a previ-

ously configured device back to its virgin state. Erasure

is automatically performed by the programming hard-

ware. No special erase operation is required.

Quality and Testability

The PALCE16V8 offers a very high level of built-in qual-

ity. The erasability of the device provides a direct means

of verifying performance of all AC and DC parameters.

In addition, this verifies complete programmability and

functionality of the device to provide the highest pro-

gramming yields and post-programming functional

yields in the industry.

The register on the PALCE16V8 can be preloaded from

the output pins to facilitate functional testing of complex

state machine designs. This feature allows direct load-

ing of arbitrary states, making it unnecessary to cycle

through long test vector sequences to reach a desired

state. In addition, transitions from illegal states can be

verified by loading illegal states and observing proper

recovery.

Technology

The high-speed PALCE16V8 is fabricated with AMD’s

advanced electrically erasable (EE) CMOS process.

The array connections are formed with proven EE cells.

Inputs and outputs are designed to be compatible with

TTL devices. This technology provides strong input

clamp diodes, output slew-rate control, and a grounded

substrate for clean switching.

Security Bit

A security bit is provided on the PALCE16V8 as a deter-

rent to unauthorized copying of the array configuration

patterns. Once programmed, this bit defeats readback

and verification of the programmed pattern by a device

programmer, securing proprietary designs from com-

petitors. The bit can only be erased in conjunction with

the array during an erase cycle.

PCI Compliance

The PALCE22V10H-7/10 is fully compliant with the PCI

Local Bus Specification published by the PCI Special In-

terest Group. The PALCE22V10H-7/10’s predictable

timing ensures compliance with the PCI AC specifica-

tions independent of the design.

Electronic Signature Word

An electronic signature word is provided in the

PALCE16V8 device. It consists of 64 bits of programm-

able memory that can contain user-defined data. The

signature data is always available to the user independ-

ent of the security bit.

2-42

PALCE16V8 Family

1...4 5 678 9 10...26

中文翻译

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与PALCE16V8Q-10PI相关器件

型号	品牌	描述	获取价格	数据表
PALCE16V8Q-10PI4	AMD	EE CMOS 20-Pin Universal Programmable Array Logic	获取价格
PALCE16V8Q-10PI5	AMD	EE CMOS 20-Pin Universal Programmable Array Logic	获取价格
PALCE16V8Q-10SC	AMD	EE CMOS 20-Pin Universal Programmable Array Logic	获取价格
PALCE16V8Q-10SC/5	ETC	Electrically-Erasable PLD	获取价格
PALCE16V8Q-10SC4	AMD	EE CMOS 20-Pin Universal Programmable Array Logic	获取价格
PALCE16V8Q-10SC5	AMD	EE CMOS 20-Pin Universal Programmable Array Logic	获取价格

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