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PACDN2416CR PDF预览

PACDN2416CR

更新时间： 2024-01-12 10:14:48
品牌 Logo 应用领域
CALMIRCO /
页数 文件大小 规格书
3页 54K
描述
ESD PROTECTION ARRAYS, CHIP SCALE PACKAGE

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PACDN2416CR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：CSP包装说明：R-PBGA-B20
针数：20Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.10.00.50
风险等级：5.92最大钳位电压：14 V
配置：COMMON BIPOLAR TERMINAL, 16 ELEMENTS二极管元件材料：SILICON
二极管类型：TRANS VOLTAGE SUPPRESSOR DIODEJESD-30 代码：R-PBGA-B20
JESD-609代码：e0元件数量：16
端子数量：20封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED极性：BIDIRECTIONAL
认证状态：Not Qualified最大重复峰值反向电压：5.9 V
子类别：Transient Suppressors表面贴装：YES
技术：AVALANCHE端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

PACDN2416CR 数据手册

 浏览型号PACDN2416CR的Datasheet PDF文件第2页浏览型号PACDN2416CR的Datasheet PDF文件第3页 
PACDN2404C  
PACDN2408C  
PACDN2416C  
CALIFORNIA MICRO DEVICES  
ESD Protection Arrays, Chip Scale Package  
Features  
Applications  
• 4, 8, or 16 transient voltage suppressors in a  
single package  
• ESD protection of I/O port connections,  
such as cellular phone, PDA, internet appliance  
and PC ports  
• In-system Electrostatic Discharge (ESD)  
protection to 18kV contact discharge per  
IEC 61000-4-2 international standard  
• Protection of interface ports or IC pins which are  
exposed to high levels of ESD  
• Compact Chip Scale Package (0.65mm pitch) format  
saves board space and eases layout in space  
critical applications compared to discrete  
• ESD protection of analog video and audio R, L, V  
(right, left, video) ports  
solutions and traditional wire bonded packages  
Product Description  
The PACDN2404C, PACDN2408C and PACDN2416C  
are transient voltage suppressor arrays that provide a  
very high level of protection for sensitive electronic  
components that may be subjected to ESD. The back-to-  
back zener connections provide ESD protection in cases  
where nodes with AC signals are present.  
contact discharge method. Using the MIL-STD-883D  
(Method 3015) specification for Human Body Model  
(HBM) ESD, all pins are protected for contact discharges  
to greater than 30kV.  
The Chip Scale Package format of these devices enable  
extremely small footprints that are necessary in portable  
electronics such as cellular phones, PDAs, internet  
appliances and PCs. The large solder bumps allow for  
standard attachment to laminate boards without the use  
of underfill.  
These devices are designed and characterized to safely  
dissipate ESD strikes at levels well beyond the maxi-  
mum requirements set forth in the IEC 61000-4-2  
international standard (Level 4, 8kV contact discharge).  
All I/Os are rated at 18kV using the IEC 61000-4-2  
SCHEMATIC DIAGRAMS  
D1  
D2  
D3  
D4  
D5  
B1  
A1  
B2  
A2  
B3  
A3  
B1  
A1  
B2  
B3  
B4  
B5  
A5  
C1  
B1  
C2  
B2  
C3  
B3  
C4  
B4  
C5  
B5  
A2  
A3  
A4  
PACDN2404C  
PACDN2408C  
A1  
A2  
A3  
A4  
A5  
PACDN2416C  
STANDARD PART ORDERING INFORMATION  
Ordering Part Number  
Package  
Style  
Bumps  
Tape & Reel  
PACDN2404C/R  
PACDN2408C/R  
PACDN2416C/R  
Chip Scale  
Chip Scale  
Chip Scale  
6
10  
20  
© 2000 California Micro Devices Corp. All rights reserved.  
C1230700  
7/17/2000 215 Topaz Street, Milpitas, California 95035  
Tel: (408) 263-3214  
Fax: (408) 263-7846  
www.calmicro.com  
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