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PA7540 PEEL™ Array
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX
)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7540 is a member of the Programmable Electrically presets, clock polarity, and other features, making the
Erasable Logic (PEEL™) Array family based on ICT’s PA7540 suitable for
a
variety of combinatorial,
CMOS EEPROM technology. PEEL™ Arrays free synchronous and asynchronous logic applications. With pin
designers from the limitations of ordinary PLDs by compatibility and super-set functionality to most 24-pin
providing the architectural flexibility and speed needed for PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
today’s programmable logic designs. The PA7540 is by far implement designs that exceed the architectures of such
the most powerful 24-pin PLD available today with 20 I/O devices. The PA7540 supports speeds as fast as
pins, 2 input/global-clocks and 40 registers/latches (20 10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
buried logic cells and 20 I/O registers/latches). Its logic power consumption 80mA (55mA typical). Packaging
array implements 84 sum-of-products logic functions. The includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure 1).
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely Anachip and popular third-party development tool
flexible offering two output functions per cell (a total of 40 manufacturers provide development and programming
for all 20 logic cells). Logic cells are configurable as D, T, support for the PA7540.
and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
I/O
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
1
24
23
22
21
20
19
18
17
16
15
14
13
2 Input/
I/CLK1
I/O
VCC
I/O
2
Global Clock Pins
2
3
4
5
6
7
8
9
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
Global
Cells
I/O
I/O
5
I/O
I/O
84 (42X2)
Array Inputs
true and
6
I/O
I/O
7
I/O
I/O
8
I/O
I/O
9
I/O
I/O
2
complement
I/O
Cells
(IOC)
10
11
12
I/O
I/O
20 I/O Pins
Global Cells
I/O Cells
I/O
I/O
20
20
I/CLK1
I/O
VCC
I/O
GND
I/CLK2
10
11
12
I/O
I/O
I/O
GND
I/O
I/CLK2
Buried
logic
SOIC
I/O
I/O
Logic
Array
I/O
I/O
DIP
Logic functions
to I/O cells
Logic
I/O
I/O
A
B
C
D
Control
Cells
I/O
I/O
20
20
I/O
I/O
(LCC)
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/CLK2
4
3
2
1
28 27 26
4
3
2
1
28 27 26
4 sum terms
4 product terms
for Global Cells
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
5
6
7
8
9
10
11
25
24
23
22
21
20
19
5
6
7
8
9
10
11
25
24
23
22
21
20
19
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
80 sum terms
(four per LCC)
I/O
I/O
NC
I/O
I/O
I/O
PA7540
NC NC
08-14-002A
I/O
I/O
I/O
I/O
I/O
I/O
Logic Control Cells
12 13 14 15 16 1718
12 13 14 15 16 17 18
PLCC-JN
PLCC-J
08-14-001B
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10