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P620-05QCL PDF预览

P620-05QCL

更新时间: 2024-01-05 04:47:43
品牌 Logo 应用领域
PLL 石英晶振
页数 文件大小 规格书
8页 265K
描述
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)

P620-05QCL 数据手册

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PLL620-05/-06/-07/-08/-09  
Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal)  
Universal Low Phase Noise IC’s  
FEATURES  
PIN CONFIGURATION  
(Top View)  
100MHz to 200MHz Fundamental or 3rd  
Overtone Crystal.  
VDD  
XIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SEL0^  
SEL1^  
GND  
Output range: 100 – 200MHz (no multiplication),  
200 – 400MHz (2x multiplier), 400 – 700MHz (4x  
multiplier), or 800MHz-1GHz(PLL620-09 only, 8x  
multiplier).  
CMOS (Standard drive PLL620-07 or Selectable  
Drive PLL620-06), PECL (Enable low PLL620-08  
or Enable high PLL620-05) or LVDS output  
(PLL620-09).  
XOUT  
SEL3^  
SEL2^  
OE  
CLKC  
VDD  
CLKT  
GND  
Supports 3.3V-Power Supply.  
GND  
GND  
Available in 16-Pin (TSSOP or 3x3mm QFN)  
Note: PLL620-06 only available in 3x3mm.  
Note: PLL620-07 only available in TSSOP.  
GND  
DESCRIPTION  
The PLL620-0x family of XO IC’s is specifically  
designed to work with high frequency fundamental  
and third overtone crystals. Their low jitter and low  
phase noise performance make them well suited for  
high frequency XO requirements. They achieve very  
low current into the crystal resulting in better overall  
stability.  
12  
11  
10  
9
13  
8
7
6
5
XIN  
GND  
CLKC  
VDD  
14 PLL620-0x  
XOUT  
SEL2^  
15  
16  
CLKT  
OE  
1
2
3
4
^: Internal pull-up  
*: PLL620-06 pin 12 is output drive select (DRIVSEL)  
(0 for High Drive CMOS, 1 for Standard Drive CMOS)  
The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09.  
BLOCK DIAGRAM  
SEL  
OUTPUT ENABLE LOGICAL LEVELS  
OE  
PLL  
Part #  
OE  
State  
Q
(Phase  
0
Output enabled  
Locked  
(Default)  
Q
PLL620-08  
Oscillator  
Loop)  
1
0
Tri-state  
Tri-state  
Amplifier  
X+  
X-  
PLL620-05  
PLL620-06  
PLL620-07  
PLL620-09  
1
PLL by-pass  
Output enabled  
(Default)  
OE input: Logical states defined by PECL levels for PLL620-08  
Logical states defined by CMOS levels for PLL620-05/-06/-  
07/-09  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 1  

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