Datasheet > P4C187-70LMB

P4C187-70LMB

更新时间： 2025-07-16 08:48:39

品牌	Logo	应用领域
PYRAMID		静态存储器
页数	文件大小	规格书
12页	978K
描述
Standard SRAM, 64KX1, 70ns, CMOS, 0.290 X 0.490 INCH, LCC-22

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P4C187-70LMB 数据手册

P4C187/P4C187L

ULTRA HIGH SPEED 64K x 1

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

Three-State Output

ꢀ

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25/35/45 ns (Commercial)

– 12/15/20/25/35 /45 ns (Industrial)

TTL Compatible Output

Fully TTL Compatible Inputs

Standard Pinout (JEDEC Approved)

– 15/20/25/35/45/55/70/85 ns (Military)

Low Power Operation

– 22-Pin 300 mil DIP

– 24-Pin 300 mil SOJ

– 22-Pin 290x490 mil LCC

– 28-Pin 350x550 mil LCC

Single 5V±10% Power Supply

Data Retention with 2.0V Supply (P4C187L)

Separate Data I/O

DESCRIPTIOꢀ

TheP4C187/P4C187Lare65,536-bitultrahighspeedstatic

RAMs organized as 64K x 1. The CMOS memories require

no clocks or refreshing and have equal access and cycle

times. The RAMs operate from a single 5V ± 10% toler-

ance power supply. Data integrity is maintained for supply

voltages down to 2.0V for the Low Power version, typically

drawing 10µA.

greatly enhancing system speeds. CMOS reduces power

consumption to a low 743mW active, 193/83mW standby

for TTL/CMOS inputs and only 5.5 mW standby for the

P4C187L.

The P4C187/P4C187L are available in 22-pin 300 mil DIP,

24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-

viding excellent board level densities.

Access times as fast as 10 nanoseconds are available,

FUꢀCTIOꢀAL BLOCk DIAꢁRAM

PIꢀ COꢀFIꢁURATIOꢀS

SOJ (J4)

DIP (P3, D3, C3)

LCC conﬁgurations at end of datasheet

Revised October 2013

Document # SRAM111 REV D

12 3 4 5 6 7...12

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