Datasheet > P25C256H

P25C256H

更新时间： 2024-04-09 19:00:50

品牌	Logo	应用领域
普冉 - PUYA		/
页数	文件大小	规格书
34页	1386K
描述
SOP8(150 mil),TSSOP8,UDFN8(230.5)

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P25C256H 数据手册

P25C256H

256-Kbit Serial SPI bus EEPROM

Datasheet Rev.1.2

General Description

The P25C256H is Serial Peripheral Interface (SPI) compatible EEPROM (Electrically Erasable

Programmable Memory) device. It contains a memory array of 256 Kbits (32 Kbytes), which is organized in

64 bytes per page.

Features



Single supply voltage: 1.7 V to 5.5 V

Max clock frequency:



15MHz clock from 4.5 V to 5.5 V

5MHz clock from 1.7 V to 5.5 V



Serial Peripheral Interface (SPI) Compatible



Standard SPI: C, S#, D, Q, W#, HOLD#

Mode 0 and Mode 3

Memory array



256 Kbits of EEPROM

Page size: 64 bytes

Write



Byte/Page Write within 5ms



Additional Write lockable page (Identification Page)

Additional 128 bits Serial Number (Unique ID)



Hardware Controlled Locking of Protected Sectors by WP Pin

Transparent ECC on each group of four bytes which can correct 1 bit error

High Reliability



Endurance:

4 Million Write Cycles

100 Years

Data Retention:



Package: PDIP8,SOP8 (150mil/208mil),TSSOP8,MSOP8,DFN8,UDFN8

1/34

12 3 4 5 6 7...34

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