Datasheet > P0340WQLC-T

P0340WQLC-T

更新时间： 2022-12-16 10:34:25

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Tentative Product Specification

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数据手册

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P0340WQLC-T 数据手册

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1.8V

2.5V

Normal display

OTP program

VDC_ENB=1, VDDD is input. (Input range = 1.6V~2.75V)

A power supply for the Digital circuit. (1.5V~3.6V)

32 VCC

Digital ground pin. It must connect to external ground.

33 VSSD

Reset pin. Setting either pin low initializes the LSI. Must be reset

after power is supplied. (Normally pull high)

34 NRESET

35 NCS

Serial Interface chip enable pin. (Normally pull high)

Serial Interface clock input pin. (Normally pull high)

Serial Interface data line. (Normally pull high)

Data enable:

36 SCL

37 SDA

When VSYNC+HSYNC+DE mode,

DE=H: Data enable, DE=L: Data disable (Black). (Normally pull low)

Frame synchronizing signal.

38 DE

If VSPL=0: Active low.

If VSPL=1: Active high.

39 VSYNC

40 HSYNC

Line synchronizing signal.

If HSPL=0: Active low.

If HSPL=1: Active high.

Dot clock signal.

If DPL=0: Data are input on the rising edge of DOTCLK.

If DPL=1: Data are input on the falling edge of DOTCLK.

Digital data input. DX0 is LSB and DX7 is MSB. (Normally pull low)

41 DCLK

42 D27

43 D26

44 D25

45 D24

46 D23

47 D22

48 D21

49 D20

50 D17

51 D16

52 D15

53 D14

54 D13

55 D12

56 D11

57 D10

58 D07

1. If parallel RGB input mode is used, D0X, D1X, and D2X indicate R,

G, and B data in turn.

2. If serial RGB or RGBD or CCIR601 or CCIR656 input mode is

selected, only D07~D00 are used, and others short to GND.

DX7~DX0 has 8-bit width, respectively to compose 16,777,216

color and 256 gray scale of 1 pixel.

1...13 14 151617 18 19 20

中文翻译

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