Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Logic Cells (continued))
COUT
CARRY
A4
A3
A4
A3
A2
QLUT3
F3
F2
C
C
Q3
Q2
Q1
A1
D3
D2
A2
A1
WD3
WD2
REG3
CARRY
SR EN
A3
A2
A1
O4
PFU_NAND
QLUT2
A4
O3
O2
A0
A0
REG2
C
CARRY
SR EN
B4
B3
B4
B3
B2
O1
O0
F1
F0
PFU_MUX
PFU_XOR
QLUT1
D1
D0
C
C
REG1
WD1
WD0
B1
B2
B1
SR EN
CARRY
B3
B2
B1
T
T
T
T
T
T
Q0
QLUT0
REG0
B4
B0
B0
SR EN
CIN
C
C
C0
LSR
GSR
T
T
C
WD[3:0]
CK
C
C
C
CKEN
TRI
5-4573(F)
Key: C = controlled by configuration RAM.
Figure 3. Simplified PFU Diagram
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The ports
are referenced with a two- to four-character suffix to a
PFU’s location. As mentioned, there are two 5-bit input
data buses (A[4:0] and B[4:0]) to the LUT, one 4-bit
input data bus (WD[3:0]) to the latches/FFs, and an
output data bus (O[4:0]).
found in each PLC are also shown, although they actu-
ally reside external to the PFU.
Each latch/FF can accept data from the LUT. Alterna-
tively, the latches/FFs can accept direct data from
WD[3:0], eliminating the LUT delay if no combinatorial
function is needed. The LUT outputs can bypass the
latches/FFs, which reduces the delay out of the PFU. It
is possible to use the LUT and latches/FFs more or
less independently. For example, the latches/FFs can
be used as a 4-bit shift register, and the LUT can be
used to detect when a register has a particular pattern
in it.
Figure 3 shows the four latches/FFs (REG[3:0]) and the
64-bit look-up table (QLUT[3:0]) in the PFU. The PFU
does combinatorial logic in the LUT and sequential
logic in the latches/FFs. The LUT is static random
access memory (SRAM) and can be used for read/
write or read-only memory. The eight 3-state buffers
6
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