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NT256D64S88A0G-75B PDF预览

NT256D64S88A0G-75B

更新时间: 2024-02-25 04:54:50
品牌 Logo 应用领域
其他 - ETC 动态存储器双倍数据速率
页数 文件大小 规格书
14页 184K
描述
184pin One Bank Unbuffered DDR SDRAM MODULE

NT256D64S88A0G-75B 数据手册

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NT256D64S88A0G  
256MB : 32M x 64  
PC2100 / PC1600 Unbuffered DIMM  
184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 32Mx8 SDRAM  
Features  
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module  
• 32Mx64 Double Data Rate (DDR) SDRAM DIMM  
• Performance :  
• DRAM DLL aligns DQ and DQS transitions with clock transitions.  
Also aligns QFC transitions with clock during Read cycles  
• Address and control signals are fully synchronous to positive  
clock edge  
PC1600  
- 8B  
2
PC2100  
• Programmable Operation:  
Unit  
Speed Sort  
- 75B  
- 7K  
2
- DIMM  
Latency: 2, 2.5  
CAS  
DIMM  
Latency  
2.5  
133  
7.5  
CAS  
- Burst Type: Sequential or Interleave  
- Burst Length: 2, 4, 8  
f CK Clock Frequency  
t CK Clock Cycle  
100  
10  
133  
7.5  
266  
MHz  
ns  
- Operation: Burst Read and Write  
• Auto Refresh (CBR) and Self Refresh Modes  
• Automatic and controlled precharge commands  
• 13/10/2 Addressing (row/column/bank)  
• 7.8 µs Max. Average Periodic Refresh Interval  
• Serial Presence Detect  
f DQ DQ Burst Frequency  
200  
266  
MHz  
• Intended for 100 MHz and 133 MHz applications  
• Inputs and outputs are SSTL-2 compatible  
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2  
• Single Pulsed  
interface  
RAS  
• SDRAMs have 4 internal banks for concurrent operation  
• Module has one physical bank  
• Gold contacts  
• SDRAMs in 66-pin TSOP Type II Package  
• Differential clock inputs  
• Data is read or written on both clock edges  
Description  
NT256D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),  
organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR  
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use  
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all  
devices on the DIMM.  
Prior to any access operation, the device  
latency and burst type/ length/operation type must be programmed into the DIMM by  
CAS  
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.  
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common  
design files minimizes electrical variation between suppliers.  
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD  
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.  
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.  
Ordering Information  
Part Number  
Speed  
143MHz (7ns @ CL = 2.5 )  
133MHz (7.5ns @ CL= 2 )  
133MHz (7.5ns @ CL= 2.5 )  
100MHz (10ns @ CL = 2 )  
125MHz (8ns @ CL = 2.5 )  
100MHz (10ns @ CL = 2 )  
Organization  
32Mx64  
Leads  
Gold  
Power  
2.5V  
NT256D64S88A0G-7K  
PC2100  
PC2100  
PC1600  
NT256D64S88A0G –75B  
NT256D64S88A0G –8B  
Preliminary 08 / 2001  
1
© NANYA TECHNOLOGY CORP.  
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.  

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