Datasheet > NPIC6C4894-Q100

NPIC6C4894-Q100

更新时间： 2024-09-25 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
21页	949K
描述
Power logic 12-bit shift register; open-drain outputs

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NPIC6C4894-Q100 数据手册

NPIC6C4894-Q100

Power logic 12-bit shift register; open-drain outputs

Rev. 1 — 17 April 2014

Product data sheet

1. General description

The NPIC6C4894-Q100 is a 12-stage serial shift register. It has a storage latch associated

with each stage for strobing data from the serial input (D) to the parallel open-drain

outputs (QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data

in each shift register stage is transferred to the storage register when the latch enable (LE)

input is HIGH. Data in the storage register drives the gate of the output extended-drain

NMOS transistor whenever the output enable input (OE) is HIGH. A LOW on OE causes

the outputs to assume a high-impedance OFF-state. Operation of the OE input does not

affect the state of the registers. Two serial outputs (QS1 and QS2) are available for

cascading a number of NIC6C4894-Q100 devices. Serial data is available at QS1 on

positive-going clock edges to allow high-speed operation in cascaded systems with a fast

clock rise time. The same serial data is available at QS2 on the next negative going clock

edge. It is used for cascading NPIC6C4894-Q100 devices when the clock has a slow rise

time. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS

transistors designed for use in systems that require moderate load power such as LEDs.

Integrated voltage clamps in the outputs, provide protection against inductive transients.

This protection makes the device suitable for power driver applications such as relays,

solenoids and other low-current or medium-voltage loads.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +125 C

 Low R_DSon

 12 Power EDNMOS transistor outputs of 100 mA continuous current

 250 mA current limit capability

 Output clamping voltage 33 V

 30 mJ avalanche energy capability

 Low power consumption

 Latch-up performance exceeds 100 mA per JESD 78 Class II level A

 ESD protection:

 HBM AEC-Q100-002 revision D class H2 exceeds 2500 V

 CDM AEC-Q100-011 revision C1 class C6 exceeds 1000 V

12 3 4 5 6 7...21

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与NPIC6C4894-Q100相关器件

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NPIC6C596	NEXPERIA	获取价格	Power logic 8-bit shift register; open-drain outputs
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