NIS5101
SMART HotPlugt IC/Inrush
Limiter/Circuit Breaker
The SMART HotPlug Integrated Circuit combines the control
function and power FET into a single IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed to allow safe insertion and removal of
electronic equipment to −48 V backplanes. This chip features
simplicity of use combined with an integrated solution.
The SMART HotPlug includes user selectable undervoltage and
overvoltage lockout levels. It also has adjustable current limiting that
can be reduced from the maximum level with a single resistor.
Operation at the maximum current level requires no extra external
components. An internal temperature shutdown circuit greatly
increases the reliability of this device.
http://onsemi.com
MARKING
DIAGRAM
8
S−PAK
NIS5101EX
AYWWG
EX SUFFIX
CASE 553AA
1
7
Features
• Integrated Power Device
• 100 V Operation
X
= 1 for Thermal Latch or
• Thermal Limit Protection
• Adjustable Current Limit
• No External Current Shunt Required
• Undervoltage and Overvoltage Lockouts
• 6.5 A Continuous Operation
• UIS Rated
2 for Thermal Auto−retry
= Assembly Location
= Year
A
Y
WW = Work Week
= Pb−Free Device
G
ORDERING INFORMATION
• Main/Mirror MOSFET Current Ratio 820:1
• Pb−Free Packages are Available
†
Device
Package
Shipping
NIS5101E1T1
S−PAK
Latch Off
2000 Units/Reel
2000 Units/Reel
Typical Applications
• VoIP (Voice over Internet Protocol) Servers
• −48 V Telecom Systems
NIS5101E1T1G
S−PAK
Latch Off
(Pb−Free)
• +24 V Wireless Base Station Power
• Central Office Switching
NIS5101E2T1
S−PAK
Auto−Retry
2000 Units/Reel
2000 Units/Reel
• Electronic Circuit Breaker
Input +
7
NIS5101E2T1G
S−PAK
Auto−Retry
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Voltage
Regulator
Thermal
Shutdown
4, 8
Drain
6
Undervoltage
Lockout
UVLO/
ENABLE
3
Current
Limit
Current
Limit
5
Overvoltage
Shutdown
OVLO
Input −
1, 2
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 21
NIS5101/D