400 and 200 Mb/s LVDS Digital
Waveform Generator/Analyzers
Specifications
These specifications are valid for the following temperature ranges – PXI: 0 to 55 °C, PCI: 0 to 45 °C.
Acquisition data delay range........................... See Exported Sample Clock Delay Range table
Acquisition data delay resolution.................... 1/256 of sample clock period for clock frequencies ≥25 MHz
or 60 ps, whichever is greater
Waveform Characteristics
Channel Characteristics
Data channels .................................................. 16
Specification
Single Data Rate (SDR)
Double Data Rate (DDR)
Comments
Using SDR, data
Triggers (inputs to the NI 656x)
Direction control Data ꢁ0..15ꢂ Per channel
of data channels
Data ꢁ0:7ꢂ
Dedicated for
Trigger types..................................................... Start trigger, pause trigger, script trigger ꢁ0:3ꢂ
(generation sessions only), reference trigger
(acquisition sessions only), advance trigger
data generation is clocked using
Data ꢁ8:15ꢂ
Dedicated for
falling edge of the
sample clock.
data acquisition
(acquisition sessions only)
Using DDR, data
is clocked using
both edges of the
sample clock.
Sources ............................................................ 1. PꢀI ꢁ0ꢂ (SMB jack connectors)
2. PꢀI ꢁ1:3ꢂ (DDC connector)
3. PXI_TRIGꢁ0:7ꢂ (PXI backplane, PXI only)
4. PXI_STAR (PXI backplane, PXI only)
5. Pattern match (acquisition sessions only)
6. Software (user function call)
Generation Signal Characteristics (data and PFI <0:3> channels)
7. Disabled (do not wait for a trigger)
Trigger detection .............................................. 1. Start trigger (edge detection: rising or falling)
2. Pause trigger (level detection: high or low)
3. Script trigger ꢁ0:3ꢂ (edge detection: rising or falling,
level detection: high or low)
Generation Signal Type
Generation
Data<0:15>, PFI<1:2>
PFI 0
PFI 3
LVDS
LVCMOS
LVCMOS or LVDS
(software-selectable)
voltage families
4. Reference triggers (edge detection: rising or falling)
5. Advance trigger (edge detection: rising or falling)
Minimum required trigger pulse width............ 30 ns
Destinations ..................................................... 1. PꢀI ꢁ0ꢂ (SMB jack connector)
2. PꢀI ꢁ1:3ꢂ (DDC connector)
Offset (Vos
Max
1.125 V 1.375 V
)
Differential Voltage (Vod
Min Max Typical
247 mV 454 mV 305 mV
)
Generation
Voltage Levels
Comments
Min
Typical
Generation
voltage levels
1.2 V
Into 100
differential load,
TIA/EIA-644-
compliant
3. PXI_TRIG ꢁ0:6ꢂ (PXI backplane)
You can route each of the triggers to any of the
destinations with the exception of the pause trigger.
You cannot export the pause trigger.
Events (outputs from the NI 656x)
Event types....................................................... Marker ꢁ0..3ꢂ, data active event, ready for start event,
ready for advance event, End of Record Event
Output impedance (LVDS channels)................. 100 Ω differential
Channel power-up state................................... Drivers disabled, 100 Ω differential impedance
Acquisition Signal Characteristics (data, strobe, and PFI <0:3> channels)
Destinations ..................................................... 1. PꢀI ꢁ0ꢂ (SMB jack connectors)
2. PꢀI ꢁ1:3ꢂ (DDC connector)
Acquisition
Voltage Families (V)
Data<0:15>, PFI<1:2>
and Strobe
3. PXI_TRIG ꢁ0:6ꢂ (PXI backplane)
PFI 0
PFI 3
You can route each of the events to any of the destinations
with the exception of data active events. You can route
data active events only to the PꢀI channels.
Acquisition voltage families
LVDS
LVCMOS
LVCMOS or LVDS
(software-selectable)
Miscellaneous
Acquisition
Voltage Threshold
Voltage Range
Onboard Clock Characteristics (only valid when PLL reference source is set to “none”)
ꢀrequency accuracy.......................................... 100 ppm (typical)
Temperature stability ....................................... 30 ppm (typical)
Voltage Levels
Acquisition voltage
levels (LVDS)
Max
50 mV
Min
0 V
Max
2.4 V
Comments
TIA/EIA-644-
compliant
Aging ................................................................ 5 ppm first year (typical)
Power Requirements
Maximum.......................................................... PXI: 16.4 W, PCI: 16.5 W
Input impedance............................................... 100 Ω differential
Timing Characteristics
Physical
Sample Clock
I/O Panel Connectors
Sample clock sources....................................... 1. Onboard clock (internal VCXO with divider)
2. CLK IN (SMB)
Label
External Function(s)
External sample clock, external PLL
reference input
Connector Type
SMB jack
3. PXI_STAR (PXI only)
CLK IN
4. STROBE (DDC connector) – acquisition only
Onboard clock frequency range ...................... NI 6561: 48 Hz to 100 MHz
(Settable to 200 MHz / N; 2 ≤ N ≤ 4,194,304)
NI 6562: 48 Hz to 200 MHz
(Settable to 200 MHz / N; 1 ≤ N ≤ 4,194,304)
Exported Sample Clock Delay Range
PꢀI 0
Events, triggers
SMB jack
SMB jack
CLK OUT
Exported sample clock,
exported reference clock
Digital data and
control (DDC)
Digital data channels, exported
sample clock, strobe, events, triggers
12X InfiniBand
Sample Clock Frequency (ƒ)
Delay Range (Sample Clock Period)
50 MHz ꢁ ƒ ꢁ maximum clock rate
0 to 1 sample clock period
Dimensions....................................................... PXI: Single 3U CompactPCI slot, PXI-compatible
PCI: 12.6 by 35.5 cm (4.96 by 13.9 in.)
0 to 1 sample clock period except
[0.25 (0.25 - 5 ns x ƒ)] and [0.75 (0.25 - 5 ns x ƒ)]
25 MHz ꢁ ƒ ꢁ 50 MHz
Environment
Operating temperature..................................... PXI: 0 to 55 °C in all NI PXI chassis except the following:
0 to 45 °C when installed in an NI PXI-1000/B and
Exported sample clock delay resolution .......... 1/256 of sample clock period for clock frequencies ≥25 MHz
or 60 ps, whichever is greater
PXI-101x chassis. (meets IEC-60068-2-1 and IEC-60068-2-2)
PCI: 0 to 45 °C
Exported Sample Clock Jitter (Typical Using Onboard Clock)
Storage temperature........................................ -20 to 70 °C
Relative humidity ............................................. 10 to 90%, noncondensing (meets IEC-60068-2-56)
Storage relative humidity................................. 5 to 95%, noncondensing (meets IEC-60068-2-56)
Period Jitter
19 ps (rms)
Cycle-to-Cycle Jitter
29 ps (rms)
Generation Signal Characteristics (data, DDC Clk Out LVDS, DDC Clk Out PECL,
and PFI <0:3> channels)
Compliance
Safety
Data channel-to-channel skew ........................ 215 (typical across all data channels and PꢀI ꢁ1:2ꢂ)
Maximum data channel toggle rate ................ NI 6561: 100 MHz; NI 6562: 200 MHz
Data position modes ........................................ Rising edge, falling edge, delayed relative to sample clock
Generation data delay range ........................... See Exported Sample Clock Delay Range table
Generation data delay resolution .................... 1/256 of sample clock period for clock frequencies ≥25 MHz
or 60 ps, whichever is greater
NI 656x devices meet the requirements of the following standards for safety and electrical equipment for
measurement, control, and laboratory use:
IEC 61010-1, EN 61010-1
UL 3111-1, UL 61010B-1
CAN/CSA C22.2 No. 1010.1
Note: ꢀor full EMC compliance, you must operate this device with shielded cabling. In addition, you must install
all covers and filler panels. See the Declaration of Conformity (DoC) for this product for any additional
regulatory compliance information. To obtain the DoC for this product, visit ni.com/hardref.nsf.
Acquisition Signal Characteristics (data, strobe, and PFI <0:3> channels)
Data channel-to-channel skew ........................ 600 ps for sample clock rates ꢁ25
330 ps for sample clock rates ꢂ25 MHz
(typical across all data channels and PꢀIꢁ1:2ꢂ)
2
National Instruments • Tel: (800) 813 3693 • info@ni.com • ni.com
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