NB675L –24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
NOT RECOMMENDED FOR NEW DESIGNS, REFER TO NB685A
VOUT
VOUT
Where ΔIL is the peak-to-peak inductor ripple
current.
(23)
VOUT
=
(1−
)
8F 2 LCOUT
V
SW
IN
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4.
VOUT
VOUT
(27)
ILP = IOUT
+
(1−
)
2FSW L
V
IN
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
PCB Layout Guide
1. CCIN and GND. The high current paths (GND,
IN, and SW) should be placed very close to
the device with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and GND pins as possible. Place the
Cap close to VCC if the distance is long. And
place >3 Vias if via is required to reduce the
leakage inductance.
VOUT
V
VOUT
=
(1− OUT )RESR
(24)
FSW L
V
IN
Maximum output capacitor limitation should be
also considered in design application. NB675L
has an around 1.6ms soft-start time period. If the
output capacitor value is too high, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value Co_max can be
limited approximately by:
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Keep the IN and GND pads connected with
large copper and use at least two layers for
IN and GND trace to achieve better thermal
performance. Also, add several Vias with
10mil_drill/18mil_copper_width close to the
IN and GND pads to help on thermal
dissipation.
CO_MAX = (ILIM_ AVG −IOUT )T / VOUT
(25)
ss
Where, ILIM_AVG is the average start-up current
during soft-start period. Tss is the soft-start time.
Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger-value inductor will have a larger physical
footprint, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductance value is to design the peak-to-
peak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Note
Please refer to the PCB Layout Application Note
for more details.
VOUT
SW IL
VOUT
(26)
L =
(1−
)
F
V
IN
NB675L Rev. 1.1
1/19/2020
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2023 MPS. All Rights Reserved.
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