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NB3L553 PDF预览

NB3L553

更新时间: 2024-10-02 03:47:03
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
6页 75K
描述
2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer

NB3L553 数据手册

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NB3L553  
2.5 V / 3.3 V / 5.0 V  
1:4 Clock Fanout Buffer  
Description  
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for  
clock distribution in mind. The NB3L553 specifically guarantees low  
output−to−output skew. Optimal design, layout and processing  
minimize skew within a device and from device to device.  
http://onsemi.com  
MARKING DIAGRAMS*  
The output enable (OE) pin tri−states the outputs when low.  
8
8
Features  
1
3L553  
ALYW  
G
Input/Output Clock Frequency up to 200 MHz  
Low Skew Outputs (35 ps)  
SOIC−8  
D SUFFIX  
CASE 751  
1
Output Enable Mode Three−States Outputs  
3N553 = Specific Device Code  
Operating Range: V = 2.375 V to 5.25 V  
DD  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
Ideal for Networking Clocks  
Packaged in 8−pin SOIC  
Industrial Temperature Range  
These are Pb−Free Devices  
1
Q1  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
Q2  
CLK  
XX = Specific Device Code  
= Date Code  
Q3  
M
(Note: Microdot may be in either location)  
Q4  
*For additional marking information, refer to  
Application Note AND8002/D.  
PINOUT  
OE  
1
2
3
4
8
7
6
5
Figure 1. Block Diagram  
OE  
Q3  
Q2  
V
DD  
Q0  
Q1  
GND  
I
CLK  
ORDERING INFORMATION  
Device  
Package  
Shipping  
NB3L553DG  
SOIC−8  
98 Units/Rail  
(Pb−Free)  
NB3L553DR2G  
SOIC−8  
(Pb−Free)  
2500/Tape & Reel  
1000/Tape & Reel  
NB3L553MNR4G* DFN−8  
(Pb−Free)  
*Contact Sales Representative  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 0  
NB3L553/D  

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