Datasheet > NB3L8504S_16

NB3L8504S_16

更新时间： 2024-10-03 01:09:39

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	249K
描述
1:4 Differential Input to LVDS Fanout Buffer / Translator

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数据手册

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NB3L8504S_16 数据手册

NB3L8504S

2.5 V / 3.3 V 1:4 Differential

Input to LVDS Fanout Buffer

/ Translator

Description

www.onsemi.com

MARKING

The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator

with OE control for each differential output. The differential inputs

which can be driven by either a differential or single−ended input, can

accept various logic level standards such as LVPECL, LVDS, HSTL,

HCSL and SSTL. These signals are then translated to four identical

LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is

ideal for Clock distribution applications that require low skew.

The NB3L8504S is offered in the TSSOP−16 package.

DIAGRAM*

TSSOP−16

DT SUFFIX

CASE 948F

NB3L

8504

ALYWG

Features

• Four Differential LVDS Outputs

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Each Differential Output has OE Control

• 700 MHz Maximum Output Frequency

• 660 ps Max Output Rise and Fall Times, LVCMOS

• Translates Differential Input to LVDS Levels

• Additive Phase Jitter RMS: < 100 fs Typical

• 50 ps Maximum Output Skew

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

• 350 ps Maximum Part−to−part Skew

• 1.3 ns Maximum Propagation Delay

• Operating Range: V = 2.5 V 5% or 3.3 V 10%

• −40°C to +85°C Ambient Operating Temperature

• 16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm

• These are Pb−Free Devices

Applications

• Telecom

• Ethernet

• Networking

• SONET

CLK

Figure 1. Logic Diagram

ORDERING INFORMATION

See detailed ordering and shipping information on page 9 of

this data sheet.

Publication Order Number:

April, 2016 − Rev. 2

NB3L8504S/D

12 3 4 5 6 7...11

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