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N9201A PDF预览

N9201A

更新时间: 2024-09-29 05:51:55
品牌 Logo 应用领域
安捷伦 - AGILENT 测试
页数 文件大小 规格书
4页 111K
描述
Array Structure Parametric Test Option

N9201A 数据手册

 浏览型号N9201A的Datasheet PDF文件第2页浏览型号N9201A的Datasheet PDF文件第3页浏览型号N9201A的Datasheet PDF文件第4页 
Agilent N9201A  
Array Structure Parametric Test Option  
Technical Overview  
Introduction  
The Agilent N9201A Parametric Test  
Option offers high throughput para-  
metric measurement capability for  
a variety of addressable array test  
structures (e.g. passive array, active  
The N9201A is able to provide a  
The decreasing size of features on  
integrated circuits (45 nm and smaller)  
is driving the need for new parametric  
test capabilities. These capabilities  
must accommodate the advanced test  
structures developed for fast yield  
ramp up in process integration as well  
as process monitoring in semiconduc-  
tor manufacturing.  
maximum of 48 signal lines using the  
extended path ports of the 4070/4080  
test head. This can be any combina-  
tion of available SMUs, digital outputs,  
array and clocked latched active array) and DC power source outputs. The  
with synchronized mixed operation of  
DC SMUs and digital outputs. Digital  
outputs (parallel, serial, or clock sig-  
nals) are used for the address decoder  
that is built into addressable array test  
structures. This allows the selection  
of the specific array element to be  
measured. DC SMUs measure the DC  
voltage and current parameters of  
selected array elements.  
signals pass through the 4070/4080  
test head down to the probe card.  
The N9201A is controlled by SPECS  
(Semiconductor Process Evaluation  
Core Software), a test shell environ-  
ment for the 4070 Series and 4080  
Series. The N9201A can be provided  
as an upgrade for existing 4070 Series  
and 4080 Series users.  
High-throughput measurement of high-  
volume parametric data is required to  
shorten the time for ramping up the  
process yield. This is accomplished by  
statistically analyzing and correcting  
the cause of wide range of process  
performance variations across a 300  
mm wafer. Advanced test structures,  
addressable array test structures that  
contain address decoder circuitry, and  
a large number of test array elements  
with fewer probing pads and silicon  
area have been developed by major  
semiconductor manufacturers for this  
purpose.  
The DC power source is used for  
applying the power supply voltage (Vdd)  
to the address decoder logic circuitry  
that is built-in the addressable array  
test structures.  

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