Datasheet > N02L83W2A

N02L83W2A

更新时间： 2022-12-16 18:17:28

品牌	Logo	应用领域
安森美 - ONSEMI		静态存储器
页数	文件大小	规格书
10页	170K
描述
2Mb Ultra-Low Power Asynchronous CMOS SRAM 256K × 8 bit

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数据手册

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N02L83W2A 数据手册

N02L83W2A

Functional Block Diagram

Word

Address

Inputs

Address

Decode

Logic

A - A

Input/

Output

Mux

Page

16K Page

x 16 word

x 8 bit

Address

Inputs

Address

A - A

Decode

Logic

and

I/O - I/O

RAM Array

Buffers

CE1

CE2

Control

Logic

Functional Description

I/O₀- I/O₇

CE1

CE2

MODE

POWER

Standby¹

Write²

X²

High Z

Standby

Active

Data In

Data Out

High Z

Active

Read

Active

1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated

from any external influence and disabled from exerting any influence externally.

2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

Capacitance

Item

Symbol

C_IN

Test Condition

Min

Max

Unit

V_IN= 0V, f = 1 MHz, T_A= 25^oC

Input Capacitance

I/O Capacitance

C_I/O

1. These parameters are verified in device characterization and are not 100% tested

Rev. 8 | Page 2 of 10 | www.onsemi.com

123 4 5 6 7...10

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