Datasheet > 存储 > SRAM> N02L163WC2AB-55I

N02L163WC2AB-55I

更新时间： 2024-01-19 20:36:29

品牌	Logo	应用领域
AMI		静态存储器
页数	文件大小	规格书
11页	185K
描述
Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, BGA-48

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N02L163WC2AB-55I 数据手册

AMI Semiconductor, Inc.

Functional Block Diagram

N02L163WC2A

Word

Address

Inputs

Address

Decode

Logic

A0 - A3

Input/

Page

32K Page

x 16 word

x 16 bit

Address

Inputs

Output

I/O0 - I/O7

Mux

Address

Decode

Logic

A4 - A16

and

RAM Array

Buffers

I/O8 - I/O15

CE1

CE2

Control

Logic

Functional Description

CE1

CE2

MODE

POWER

I/O₀- I/O₁₅

Standby²

X³

L¹

High Z

Data In

Data Out

High Z

Standby

Active

Standby

Write³

Read

Active

1. When UB and LB are in select mode (low), I/O₀- I/O₁₅are affected as shown. When LB only is in the select mode only I/O₀- I/O₇

are affected as shown. When UB is in the select mode only I/O₈- I/O₁₅are affected as shown.

2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally

isolated from any external influence and disabled from exerting any influence externally.

3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

Capacitance

Item

Symbol

C_IN

Test Condition

Min

Max

Unit

V_IN= 0V, f = 1 MHz, T_A= 25^oC

Input Capacitance

I/O Capacitance

C_I/O

1. These parameters are verified in device characterization and are not 100% tested

(DOC# 14-02-013 REV H ECN# 01-1270)

The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.

1 234 5 6 7...11

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