Datasheet > 存储 > OTP ROM> MX27C2048QC-55

MX27C2048QC-55

更新时间： 2024-02-21 03:31:09

品牌	Logo	应用领域
旺宏电子 - Macronix		存储内存集成电路 PC 可编程只读存储器 OTP只读存储器电动程控只读存储器
页数	文件大小	规格书
18页	766K
描述
2M-BIT [256Kx8/128x16] CMOS EPROM

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技术参数
数据手册

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MX27C2048QC-55 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LPCC	包装说明：	QCCJ, LDCC44,.7SQ
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.61	Is Samacsys：	N
最长访问时间：	55 ns	I/O 类型：	COMMON
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
长度：	16.5862 mm	内存密度：	2097152 bit
内存集成电路类型：	OTP ROM	内存宽度：	16
功能数量：	1	端子数量：	44
字数：	131072 words	字数代码：	128000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX16
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	4.57 mm	最大待机电流：	0.0001 A
子类别：	OTP ROMs	最大压摆率：	0.05 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	16.5862 mm
Base Number Matches：	1

MX27C2048QC-55 数据手册

MX27C2100/27C2048

VIL(for MX27C2048), OE at VIL, CE at VIH(for

MX27C2100) and VPP at its programming voltage.

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C2100/2048

AUTO IDENTIFY MODE

When the MX27C2100/2048 is delivered, or it is

erased, the chip has all 2M bits in the "ONE", or HIGH

state. "ZEROs" are loaded into the MX27C2100/2048

through the procedure of programming.

Theautoidentifymodeallowsthereadingoutofabinary

code from an EPROM that will identify its manufacturer

and device type. This mode is intended for use by

programming equipment for the purpose of

automatically matching the device to be programmed

with its corresponding programming algorithm. This

mode is functional in the 25°C ± 5°C ambient

temperature range that is required when programming

the MX27C2100/2048.

Forprogramming, thedatatobeprogrammedisapplied

with 16 bits in parallel to the data pins.

VCCmustbeappliedsimultaneouslyorbeforeVPP,and

removed simultaneously or after VPP. When

programming an MXIC EPROM, a 0.1uF capacitor is

required across VPP and ground to suppress spurious

voltage transients which may damage the device.

To activate this mode, the programming equipment

mustforce12.0±0.5VonaddresslineA9ofthedevice.

Two identifier bytes may then be sequenced from the

device outputs by toggling address line A0 from VIL to

VIH. All other address lines must be held at VIL during

auto identify mode.

FAST PROGRAMMING

Thedeviceissetupinthefastprogrammingmodewhen

the programming voltage VPP = 12.75V is applied, with

VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm

is shown in Figure 1). The programming is achieved by

applying a single TTL low level 100us pulse to the PGM

inputafteraddressesanddatalinearestable. Ifthedata

is not verified, an additional pulse is applied for a

maximum of 25 pulses. This process is repeated while

sequencing through each address of the device. When

the programming mode is completed, the data in all

address is verified at VCC = VPP = 5V ±10%.

Byte 0 ( A0 = VIL) represents the manufacturer code,

andbyte1(A0=VIH), thedeviceidentifiercode. Forthe

MX27C2100/2048, these two identifier bytes are given

intheModeSelectTable. Allidentifiersformanufacturer

and device codes will possess odd parity, with the MSB

(Q15) defined as the parity bit.

READ MODE

The MX27C2100/2048 has two control functions, both

ofwhichmustbelogicallysatisfiedinordertoobtaindata

at the outputs. Chip Enable (CE) is the power control

andshouldbeusedfordeviceselection. OutputEnable

(OE) is the output control and should be used to gate

datatotheoutputpins, independentofdeviceselection.

Assuming that addresses are stable, address access

time(tACC)isequaltothedelayfromCEtooutput(tCE).

DataisavailableattheoutputstOEafterthefallingedge

of OE's, assuming that CE has been LOW and

addresses have been stable for at least tACC - t OE.

PROGRAM INHIBIT MODE

ProgrammingofmultipleMX27C2100/2048'sinparallel

with different data is also easily accomplished by using

theProgramInhibitMode. ExceptforCEandOE,alllike

inputs of the parallel MX27C2100/2048 may be

common. A TTL low-level program pulse applied to an

MX27C2100/2048 CE input with VPP = 12.5 ±0.5 V will

program the MX27C2100/2048. A high-level CE input

inhibits the other MX27C2100/2048s from being

programmed.

WORD-WIDE MODE

PROGRAM VERIFY MODE

With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present

data Q0-7 and outputs Q8-15 present data Q8-15, after

CE and OE are appropriately enabled.

Verification should be performed on the programmed

bits to determine that they were correctly programmed.

The verification should be performed with OE and CE at

P/N: PM0158

REV. 4.3, AUG. 22, 2001

1 234 5 6 7...18

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