Datasheet > MX25V512E

MX25V512E

更新时间： 2024-04-09 18:59:28

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MX25V512E 数据手册

MX25V512E

HARDWARE FEATURES

• SCLK Input

Serial clock input

• SI/SIO0

- Serial Data Input or Serial Data Output for Dual output mode

• SO/SIO1

- Serial Data Output or Serial Data Output for Dual output mode

• WP# pin

- Hardware write protection

• HOLD# pin

- pause the chip without diselecting the chip

• PACKAGE

- 8-USON (2x3mm)

- 8-pin TSSOP (173mil)

- 8-pin SOP (150mil)

- All devices are RoHS compliant and Halogen-free

GENERAL DESCRIPTION

MX25V512E is a CMOS 524,288 bit serial Flash memory, which is conﬁgured as 65,536 x 8 internally. MX25V512E

features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus

signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device

is enabled by CS# input.

MX25V512E provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-

ﬁed page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and

erase command is executed on chip or sector (4K-bytes).

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via the WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 25uA DC cur-

rent.

The MX25V512E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

P/N: PM1734

REV. 1.4, June 07, 2016

1 2 3 456 7 8...43

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