MU9C4480A/L
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should
never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and
bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
daisy chain. /MF will be reset when the active configuration
register set is changed.
The /E input enables the device while LOW. The falling edge
registers the control signals /W, /CM, and /EC. The rising
edge locks the daisy chain, turns off the DQ pins, and clocks
the Destination and Source Segment counters. The four cycle
types enabled by /E are shown in Table 2.
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in the
chain must be tied HIGH.
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a device
cycle. /W LOW selects a Write cycle and /W HIGH selects a
Read cycle.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare cycle.
The /MA output is not qualified by /EC or /MI, and reflects
the match flag from that specific device’s Status register. /MA
will be reset when the active register set is changed.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare cycle.
The /MM output is not qualified by /EC or /MI, and reflects
the multiple match flag from that specific device’s Status
register. /MMwillberesetwhentheactiveregistersetischanged.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input enables
the /MF output to show the results of a comparison, as shown
in Figure 6 on page 14. If /EC is LOW at the falling edge of /E
in a given cycle, the /MF output is enabled. Otherwise, the
/MF output is held HIGH. The /EC signal also enables the
/MF–/MI daisy chain, which serves to select the device with
the highest-priority match in a string of LANCAMs. Tables 5a
and 5b on page 11 explain the effect of the /EC signal on a
device with or without a match in both Standard and Enhanced
modes. /EC must be HIGH during initialization.
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device (and
in the daisy chain above the device as indicated by the /FI
pin). The System Full flag is the /FF pin of the last device in the
daisy chain, and the Next Free address resides in the device
with /FI LOW and /FF HIGH. If disabled in the Control register,
the /FF output only depends on the /FI input (/FF = /FI).
DQ15–0 (Data Bus, I/O, TTL)
The DQ15–0 lines convey data, commands, and status to and
from the LANCAM. The direction and nature of the information
that flows to or from the device are controlled by /W and /CM.
When /E is HIGH, DQ15–0 go to Hi-Z.
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected to
the /FF output of the previous device in the daisy chain. The
/FI pin on the first device in a chain must be tied LOW.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on the
first cycle that /EC is registered LOW by the previous falling
edge of /E; see Figure 6 on page 14). In a daisy chain, valid
match(es) in higher priority devices are passed from the /MI
input to /MF. If the daisy chain is enabled but the match flag is
disabled in the Control register, the /MF output only depends
on the /MI input of the device (/MF=/MI). /MF is HIGH if
there is no match or when the daisy chain is disabled (/E goes
HIGH when /EC was HIGH on the previous falling edge of /E).
The System Match flag is the /MF pin of the last device in the
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 9. LANCAM ‘A’ devices
have a hardware reset that operates in parallel with the internal
Power-on-reset circuitry, and sets the device to the same
condition. For compatibility with the MU9C1480, the /RESET
pin has an internal pull-up resistor and may be leftunconnected.
The /RESET pin should be driven by TTL levels, not directly by
anRCtimeout. /EmustbekeptHIGHduring/RESET.
3
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