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MTP6P20EWC

更新时间: 2024-01-27 02:49:19
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摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲局域网
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MTP6P20EWC 数据手册

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Order this document  
by MTP6P20E/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
P–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
6.0 AMPERES  
200 VOLTS  
This advanced TMOS E–FET is designed to withstand high  
energy in the avalanche and commutation modes. The new energy  
efficient design also offers a drain–to–source diode with a fast  
recovery time. Designed for low voltage, high speed switching  
applications in power supplies, converters and PWM motor  
controls, these devices are particularly well suited for bridge circuits  
where diode speed and commutating safe operating areas are  
critical and offer additional safety margin against unexpected  
voltage transients.  
R
= 1.0 OHM  
DS(on)  
Avalanche Energy Specified  
Source–to–Drain Diode Recovery Time Comparable to a  
Discrete Fast Recovery Diode  
Diode is Characterized for Use in Bridge Circuits  
I
and V Specified at Elevated Temperature  
DSS  
DS(on)  
D
G
CASE 221A–06, Style 5  
TO–220AB  
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
Unit  
Drain–Source Voltage  
V
DSS  
200  
Vdc  
Drain–Gate Voltage (R  
GS  
= 1.0 M)  
V
DGR  
200  
Vdc  
Gate–Source Voltage — Continuous  
— Non–Repetitive (t 10 ms)  
V
± 20  
± 40  
Vdc  
Vpk  
GS  
V
GSM  
p
Drain Current — Continuous  
— Continuous @ 100°C  
— Single Pulse (t 10 µs)  
I
I
6.0  
3.9  
21  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
75  
0.6  
Watts  
W/°C  
Operating and Storage Temperature Range  
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
T , T  
stg  
55 to 150  
180  
°C  
J
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 10 Vdc, I = 6.0 Apk, L = 10 mH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
— Junction to Ambient  
R
R
1.67  
62.5  
°C/W  
°C  
θJC  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds  
T
260  
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
Motorola, Inc. 1995  

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