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MTB4N80E1 PDF预览

MTB4N80E1

更新时间： 2024-01-24 14:17:14
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲
页数 文件大小 规格书
8页 163K
描述
TMOS POWER FET 4.0 AMPERES 800 VOLTS

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MTB4N80E1 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：IN-LINE, R-PSIP-T3Reach Compliance Code：unknown
风险等级：5.75雪崩能效等级（Eas）：320 mJ
外壳连接：DRAIN配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：800 V最大漏极电流 (Abs) (ID)：4 A
最大漏极电流 (ID)：4 A最大漏源导通电阻：3 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PSIP-T3
JESD-609代码：e0元件数量：1
端子数量：3工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：IN-LINE
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：125 W
最大脉冲漏极电流 (IDM)：12 A认证状态：Not Qualified
子类别：FET General Purpose Power表面贴装：NO
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子位置：SINGLE晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

MTB4N80E1 数据手册

 浏览型号MTB4N80E1的Datasheet PDF文件第2页浏览型号MTB4N80E1的Datasheet PDF文件第3页浏览型号MTB4N80E1的Datasheet PDF文件第4页浏览型号MTB4N80E1的Datasheet PDF文件第6页浏览型号MTB4N80E1的Datasheet PDF文件第7页浏览型号MTB4N80E1的Datasheet PDF文件第8页 
10  
8
500  
400  
300  
200  
1000  
V
= 400 V  
= 4 A  
= 10 V  
= 25°C  
DD  
QT  
I
V
T
D
GS  
V
GS  
J
Q1  
Q2  
6
100  
t
f
4
I
T
= 4 A  
= 25°C  
D
J
t
t
d(off)  
t
r
2
100  
0
V
Q3  
6
DS  
d(on)  
0
10  
0
12  
18  
24  
30  
36  
1
10  
R , GATE RESISTANCE (OHMS)  
G
100  
Q
, TOTAL GATE CHARGE (nC)  
G
Figure 8. Gate–To–Source and Drain–To–Source  
Voltage versus Total Charge  
Figure 9. Resistive Switching Time  
Variation versus Gate Resistance  
DRAIN–TO–SOURCE DIODE CHARACTERISTICS  
4.0  
3.6  
3.2  
2.8  
2.4  
2.0  
1.6  
1.2  
0.8  
0.4  
0
V
= 0 V  
GS  
T
= 25  
°C  
J
0.50  
0.54  
0.58  
0.62  
0.66  
0.70  
0.74  
0.78  
0.82  
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)  
SD  
Figure 10. Diode Forward Voltage versus Current  
SAFE OPERATING AREA  
The Forward Biased Safe Operating Area curves define  
the maximum simultaneous drain–to–source voltage and  
drain current that a transistor can handle safely when it is for-  
ward biased. Curves are based upon maximum peak junc-  
able operation, the stored energy from circuit inductance dis-  
sipated in the transistor while in avalanche must be less than  
the rated limit and adjusted for operating conditions differing  
from those specified. Although industry practice is to rate in  
terms of energy, avalanche energy capability is not a con-  
stant. The energy rating decreases non–linearly with an in-  
crease of peak current in avalanche and peak junction  
temperature.  
tion temperature and a case temperature (T ) of 25°C. Peak  
C
repetitive pulsed power limits are determined by using the  
thermal response data in conjunction with the procedures  
discussed in AN569, “Transient Thermal Resistance–Gener-  
al Data and Its Use.”  
Although many E–FETs can withstand the stress of drain–  
to–source avalanche at currents up to rated pulsed current  
Switching between the off–state and the on–state may tra-  
verse any load line provided neither rated peak current (I  
)
DM  
) is exceeded and the transition time  
(I  
), the energy rating is specified at rated continuous cur-  
DM  
nor rated voltage (V  
DSS  
rent (I ), in accordance with industry custom. The energy rat-  
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-  
r f  
ing must be derated for temperature as shown in the  
accompanying graph (Figure 12). Maximum energy at cur-  
aged over a complete switching cycle must not exceed  
(T  
– T )/(R ).  
J(MAX)  
C
θJC  
rents below rated continuous I can safely be assumed to  
A Power MOSFET designated E–FET can be safely used  
D
in switching circuits with unclamped inductive loads. For reli-  
Motorola TMOS Power MOSFET Transistor Device Data  
equal the values indicated.  
5
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